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author | Alec Roelke <ar4jc@virginia.edu> | 2017-06-15 15:33:25 -0400 |
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committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-11 03:37:04 +0000 |
commit | 63d4005a29dea37e0219444a3de2cdb25289fdfb (patch) | |
tree | 88bf3070e642da6594cb51b9dfc5b2cf63b93bdb /src/arch/riscv/registers.hh | |
parent | 91f965dd5708eb365f1b28d30f2c3f012519b1c2 (diff) | |
download | gem5-63d4005a29dea37e0219444a3de2cdb25289fdfb.tar.xz |
arch-riscv: Restructure ISA description
This patch restructures the RISC-V ISA description to use fewer classes
and improve its ability to be extended with nonstandard extensions in
the future. It also cleans up the disassembly for some of the CSR and
system instructions by removing source and destination registers for
instructions that don't have any.
[Fix class UImmOp to have an "imm" member rather than "uimm".]
[Update disassembly generation for new RegId class.]
Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
Reviewed-on: https://gem5-review.googlesource.com/3800
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/registers.hh')
-rw-r--r-- | src/arch/riscv/registers.hh | 221 |
1 files changed, 212 insertions, 9 deletions
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index 6ae1c1691..e2b04ab84 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -49,6 +49,7 @@ #include <map> #include <string> +#include <vector> #include "arch/generic/types.hh" #include "arch/generic/vec_reg.hh" @@ -91,29 +92,37 @@ const int StackPointerReg = 2; const int GlobalPointerReg = 3; const int ThreadPointerReg = 4; const int FramePointerReg = 8; -const int ReturnValueRegs[] = {10, 11}; +const std::vector<int> ReturnValueRegs = {10, 11}; const int ReturnValueReg = ReturnValueRegs[0]; -const int ArgumentRegs[] = {10, 11, 12, 13, 14, 15, 16, 17}; +const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}; const int AMOTempReg = 32; -const char* const RegisterNames[] = {"zero", "ra", "sp", "gp", +const std::vector<std::string> IntRegNames = { + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", - "t3", "t4", "t5", "t6"}; + "t3", "t4", "t5", "t6" +}; +const std::vector<std::string> FloatRegNames = { + "ft0", "ft1", "ft2", "ft3", + "ft4", "ft5", "ft6", "ft7", + "fs0", "fs1", "fa0", "fa1", + "fa2", "fa3", "fa4", "fa5", + "fa6", "fa7", "fs2", "fs3", + "fs4", "fs5", "fs6", "fs7", + "fs8", "fs9", "fs10", "fs11", + "ft8", "ft9", "ft10", "ft11" +}; const int SyscallNumReg = ArgumentRegs[7]; -const int SyscallArgumentRegs[] = {ArgumentRegs[0], ArgumentRegs[1], +const std::vector<int> SyscallArgumentRegs = {ArgumentRegs[0], ArgumentRegs[1], ArgumentRegs[2], ArgumentRegs[3]}; const int SyscallPseudoReturnReg = ReturnValueRegs[0]; -const int NumHpmcounter = 29; -const int NumHpmcounterh = 29; -const int NumMhpmcounter = 29; -const int NumMhpmevent = 29; enum MiscRegIndex { MISCREG_USTATUS = 0x000, MISCREG_UIE = 0x004, @@ -196,6 +205,200 @@ enum MiscRegIndex { MISCREG_DSCRATCH = 0x7B2 }; +const std::map<int, std::string> MiscRegNames = { + {MISCREG_USTATUS, "ustatus"}, + {MISCREG_UIE, "uie"}, + {MISCREG_UTVEC, "utvec"}, + {MISCREG_USCRATCH, "uscratch"}, + {MISCREG_UEPC, "uepc"}, + {MISCREG_UCAUSE, "ucause"}, + {MISCREG_UBADADDR, "ubadaddr"}, + {MISCREG_UIP, "uip"}, + {MISCREG_FFLAGS, "fflags"}, + {MISCREG_FRM, "frm"}, + {MISCREG_FCSR, "fcsr"}, + {MISCREG_CYCLE, "cycle"}, + {MISCREG_TIME, "time"}, + {MISCREG_INSTRET, "instret"}, + {MISCREG_HPMCOUNTER_BASE + 0, "hpmcounter03"}, + {MISCREG_HPMCOUNTER_BASE + 1, "hpmcounter04"}, + {MISCREG_HPMCOUNTER_BASE + 2, "hpmcounter05"}, + {MISCREG_HPMCOUNTER_BASE + 3, "hpmcounter06"}, + {MISCREG_HPMCOUNTER_BASE + 4, "hpmcounter07"}, + {MISCREG_HPMCOUNTER_BASE + 5, "hpmcounter08"}, + {MISCREG_HPMCOUNTER_BASE + 6, "hpmcounter09"}, + {MISCREG_HPMCOUNTER_BASE + 7, "hpmcounter10"}, + {MISCREG_HPMCOUNTER_BASE + 8, "hpmcounter11"}, + {MISCREG_HPMCOUNTER_BASE + 9, "hpmcounter12"}, + {MISCREG_HPMCOUNTER_BASE + 10, "hpmcounter13"}, + {MISCREG_HPMCOUNTER_BASE + 11, "hpmcounter14"}, + {MISCREG_HPMCOUNTER_BASE + 12, "hpmcounter15"}, + {MISCREG_HPMCOUNTER_BASE + 13, "hpmcounter16"}, + {MISCREG_HPMCOUNTER_BASE + 14, "hpmcounter17"}, + {MISCREG_HPMCOUNTER_BASE + 15, "hpmcounter18"}, + {MISCREG_HPMCOUNTER_BASE + 16, "hpmcounter19"}, + {MISCREG_HPMCOUNTER_BASE + 17, "hpmcounter20"}, + {MISCREG_HPMCOUNTER_BASE + 18, "hpmcounter21"}, + {MISCREG_HPMCOUNTER_BASE + 19, "hpmcounter22"}, + {MISCREG_HPMCOUNTER_BASE + 20, "hpmcounter23"}, + {MISCREG_HPMCOUNTER_BASE + 21, "hpmcounter24"}, + {MISCREG_HPMCOUNTER_BASE + 22, "hpmcounter25"}, + {MISCREG_HPMCOUNTER_BASE + 23, "hpmcounter26"}, + {MISCREG_HPMCOUNTER_BASE + 24, "hpmcounter27"}, + {MISCREG_HPMCOUNTER_BASE + 25, "hpmcounter28"}, + {MISCREG_HPMCOUNTER_BASE + 26, "hpmcounter29"}, + {MISCREG_HPMCOUNTER_BASE + 27, "hpmcounter30"}, + {MISCREG_HPMCOUNTER_BASE + 28, "hpmcounter31"}, + {MISCREG_CYCLEH, "cycleh"}, + {MISCREG_TIMEH, "timeh"}, + {MISCREG_INSTRETH, "instreth"}, + {MISCREG_HPMCOUNTERH_BASE + 0, "hpmcounterh03"}, + {MISCREG_HPMCOUNTERH_BASE + 1, "hpmcounterh04"}, + {MISCREG_HPMCOUNTERH_BASE + 2, "hpmcounterh05"}, + {MISCREG_HPMCOUNTERH_BASE + 3, "hpmcounterh06"}, + {MISCREG_HPMCOUNTERH_BASE + 4, "hpmcounterh07"}, + {MISCREG_HPMCOUNTERH_BASE + 5, "hpmcounterh08"}, + {MISCREG_HPMCOUNTERH_BASE + 6, "hpmcounterh09"}, + {MISCREG_HPMCOUNTERH_BASE + 7, "hpmcounterh10"}, + {MISCREG_HPMCOUNTERH_BASE + 8, "hpmcounterh11"}, + {MISCREG_HPMCOUNTERH_BASE + 9, "hpmcounterh12"}, + {MISCREG_HPMCOUNTERH_BASE + 10, "hpmcounterh13"}, + {MISCREG_HPMCOUNTERH_BASE + 11, "hpmcounterh14"}, + {MISCREG_HPMCOUNTERH_BASE + 12, "hpmcounterh15"}, + {MISCREG_HPMCOUNTERH_BASE + 13, "hpmcounterh16"}, + {MISCREG_HPMCOUNTERH_BASE + 14, "hpmcounterh17"}, + {MISCREG_HPMCOUNTERH_BASE + 15, "hpmcounterh18"}, + {MISCREG_HPMCOUNTERH_BASE + 16, "hpmcounterh19"}, + {MISCREG_HPMCOUNTERH_BASE + 17, "hpmcounterh20"}, + {MISCREG_HPMCOUNTERH_BASE + 18, "hpmcounterh21"}, + {MISCREG_HPMCOUNTERH_BASE + 19, "hpmcounterh22"}, + {MISCREG_HPMCOUNTERH_BASE + 20, "hpmcounterh23"}, + {MISCREG_HPMCOUNTERH_BASE + 21, "hpmcounterh24"}, + {MISCREG_HPMCOUNTERH_BASE + 22, "hpmcounterh25"}, + {MISCREG_HPMCOUNTERH_BASE + 23, "hpmcounterh26"}, + {MISCREG_HPMCOUNTERH_BASE + 24, "hpmcounterh27"}, + {MISCREG_HPMCOUNTERH_BASE + 25, "hpmcounterh28"}, + {MISCREG_HPMCOUNTERH_BASE + 26, "hpmcounterh29"}, + {MISCREG_HPMCOUNTERH_BASE + 27, "hpmcounterh30"}, + {MISCREG_HPMCOUNTERH_BASE + 28, "hpmcounterh31"}, + + {MISCREG_SSTATUS, "sstatus"}, + {MISCREG_SEDELEG, "sedeleg"}, + {MISCREG_SIDELEG, "sideleg"}, + {MISCREG_SIE, "sie"}, + {MISCREG_STVEC, "stvec"}, + {MISCREG_SSCRATCH, "sscratch"}, + {MISCREG_SEPC, "sepc"}, + {MISCREG_SCAUSE, "scause"}, + {MISCREG_SBADADDR, "sbadaddr"}, + {MISCREG_SIP, "sip"}, + {MISCREG_SPTBR, "sptbr"}, + + {MISCREG_HSTATUS, "hstatus"}, + {MISCREG_HEDELEG, "hedeleg"}, + {MISCREG_HIDELEG, "hideleg"}, + {MISCREG_HIE, "hie"}, + {MISCREG_HTVEC, "htvec"}, + {MISCREG_HSCRATCH, "hscratch"}, + {MISCREG_HEPC, "hepc"}, + {MISCREG_HCAUSE, "hcause"}, + {MISCREG_HBADADDR, "hbadaddr"}, + {MISCREG_HIP, "hip"}, + + {MISCREG_MVENDORID, "mvendorid"}, + {MISCREG_MARCHID, "marchid"}, + {MISCREG_MIMPID, "mimpid"}, + {MISCREG_MHARTID, "mhartid"}, + {MISCREG_MSTATUS, "mstatus"}, + {MISCREG_MISA, "misa"}, + {MISCREG_MEDELEG, "medeleg"}, + {MISCREG_MIDELEG, "mideleg"}, + {MISCREG_MIE, "mie"}, + {MISCREG_MTVEC, "mtvec"}, + {MISCREG_MSCRATCH, "mscratch"}, + {MISCREG_MEPC, "mepc"}, + {MISCREG_MCAUSE, "mcause"}, + {MISCREG_MBADADDR, "mbadaddr"}, + {MISCREG_MIP, "mip"}, + {MISCREG_MBASE, "mbase"}, + {MISCREG_MBOUND, "mbound"}, + {MISCREG_MIBASE, "mibase"}, + {MISCREG_MIBOUND, "mibound"}, + {MISCREG_MDBASE, "mdbase"}, + {MISCREG_MDBOUND, "mdbound"}, + {MISCREG_MCYCLE, "mcycle"}, + {MISCREG_MINSTRET, "minstret"}, + {MISCREG_MHPMCOUNTER_BASE + 0, "mhpmcounter03"}, + {MISCREG_MHPMCOUNTER_BASE + 1, "mhpmcounter04"}, + {MISCREG_MHPMCOUNTER_BASE + 2, "mhpmcounter05"}, + {MISCREG_MHPMCOUNTER_BASE + 3, "mhpmcounter06"}, + {MISCREG_MHPMCOUNTER_BASE + 4, "mhpmcounter07"}, + {MISCREG_MHPMCOUNTER_BASE + 5, "mhpmcounter08"}, + {MISCREG_MHPMCOUNTER_BASE + 6, "mhpmcounter09"}, + {MISCREG_MHPMCOUNTER_BASE + 7, "mhpmcounter10"}, + {MISCREG_MHPMCOUNTER_BASE + 8, "mhpmcounter11"}, + {MISCREG_MHPMCOUNTER_BASE + 9, "mhpmcounter12"}, + {MISCREG_MHPMCOUNTER_BASE + 10, "mhpmcounter13"}, + {MISCREG_MHPMCOUNTER_BASE + 11, "mhpmcounter14"}, + {MISCREG_MHPMCOUNTER_BASE + 12, "mhpmcounter15"}, + {MISCREG_MHPMCOUNTER_BASE + 13, "mhpmcounter16"}, + {MISCREG_MHPMCOUNTER_BASE + 14, "mhpmcounter17"}, + {MISCREG_MHPMCOUNTER_BASE + 15, "mhpmcounter18"}, + {MISCREG_MHPMCOUNTER_BASE + 16, "mhpmcounter19"}, + {MISCREG_MHPMCOUNTER_BASE + 17, "mhpmcounter20"}, + {MISCREG_MHPMCOUNTER_BASE + 18, "mhpmcounter21"}, + {MISCREG_MHPMCOUNTER_BASE + 19, "mhpmcounter22"}, + {MISCREG_MHPMCOUNTER_BASE + 20, "mhpmcounter23"}, + {MISCREG_MHPMCOUNTER_BASE + 21, "mhpmcounter24"}, + {MISCREG_MHPMCOUNTER_BASE + 22, "mhpmcounter25"}, + {MISCREG_MHPMCOUNTER_BASE + 23, "mhpmcounter26"}, + {MISCREG_MHPMCOUNTER_BASE + 24, "mhpmcounter27"}, + {MISCREG_MHPMCOUNTER_BASE + 25, "mhpmcounter28"}, + {MISCREG_MHPMCOUNTER_BASE + 26, "mhpmcounter29"}, + {MISCREG_MHPMCOUNTER_BASE + 27, "mhpmcounter30"}, + {MISCREG_MHPMCOUNTER_BASE + 28, "mhpmcounter31"}, + {MISCREG_MUCOUNTEREN, "mucounteren"}, + {MISCREG_MSCOUNTEREN, "mscounteren"}, + {MISCREG_MHCOUNTEREN, "mhcounteren"}, + {MISCREG_MHPMEVENT_BASE + 0, "mhpmevent03"}, + {MISCREG_MHPMEVENT_BASE + 1, "mhpmevent04"}, + {MISCREG_MHPMEVENT_BASE + 2, "mhpmevent05"}, + {MISCREG_MHPMEVENT_BASE + 3, "mhpmevent06"}, + {MISCREG_MHPMEVENT_BASE + 4, "mhpmevent07"}, + {MISCREG_MHPMEVENT_BASE + 5, "mhpmevent08"}, + {MISCREG_MHPMEVENT_BASE + 6, "mhpmevent09"}, + {MISCREG_MHPMEVENT_BASE + 7, "mhpmevent10"}, + {MISCREG_MHPMEVENT_BASE + 8, "mhpmevent11"}, + {MISCREG_MHPMEVENT_BASE + 9, "mhpmevent12"}, + {MISCREG_MHPMEVENT_BASE + 10, "mhpmevent13"}, + {MISCREG_MHPMEVENT_BASE + 11, "mhpmevent14"}, + {MISCREG_MHPMEVENT_BASE + 12, "mhpmevent15"}, + {MISCREG_MHPMEVENT_BASE + 13, "mhpmevent16"}, + {MISCREG_MHPMEVENT_BASE + 14, "mhpmevent17"}, + {MISCREG_MHPMEVENT_BASE + 15, "mhpmevent18"}, + {MISCREG_MHPMEVENT_BASE + 16, "mhpmevent19"}, + {MISCREG_MHPMEVENT_BASE + 17, "mhpmevent20"}, + {MISCREG_MHPMEVENT_BASE + 18, "mhpmevent21"}, + {MISCREG_MHPMEVENT_BASE + 19, "mhpmevent22"}, + {MISCREG_MHPMEVENT_BASE + 20, "mhpmevent23"}, + {MISCREG_MHPMEVENT_BASE + 21, "mhpmevent24"}, + {MISCREG_MHPMEVENT_BASE + 22, "mhpmevent25"}, + {MISCREG_MHPMEVENT_BASE + 23, "mhpmevent26"}, + {MISCREG_MHPMEVENT_BASE + 24, "mhpmevent27"}, + {MISCREG_MHPMEVENT_BASE + 25, "mhpmevent28"}, + {MISCREG_MHPMEVENT_BASE + 26, "mhpmevent29"}, + {MISCREG_MHPMEVENT_BASE + 27, "mhpmevent30"}, + {MISCREG_MHPMEVENT_BASE + 28, "mhpmevent31"}, + + {MISCREG_TSELECT, "tselect"}, + {MISCREG_TDATA1, "tdata1"}, + {MISCREG_TDATA2, "tdata2"}, + {MISCREG_TDATA3, "tdata3"}, + {MISCREG_DCSR, "dcsr"}, + {MISCREG_DPC, "dpc"}, + {MISCREG_DSCRATCH, "dscratch"} +}; + } #endif // __ARCH_RISCV_REGISTERS_HH__ |