diff options
author | Alec Roelke <ar4jc@virginia.edu> | 2018-01-04 14:17:13 -0500 |
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committer | Alec Roelke <ar4jc@virginia.edu> | 2018-01-04 19:49:41 +0000 |
commit | 0d9f83789bada086ef0901ac30ec31954e905ede (patch) | |
tree | db2980d205be5a6d63cad95795f75c20cc11fb74 /src/arch/riscv | |
parent | 33ca06af1b9a60c21e0b6828921af406c8b230cc (diff) | |
download | gem5-0d9f83789bada086ef0901ac30ec31954e905ede.tar.xz |
arch-riscv: Remove "magic" syscall number constant
getSyscallArg() in RISC-V has an explicit check to make sure that the
register index is within the bounds of the system call register indices
vector. This patch fixes it so that it uses SyscallArgumentRegs.size()
rather than a "magic" constant that has to be updated every time
SyscallArgumentRegs is changed.
Change-Id: I2935d811177dc8028cb3df64b250ba997bc970d8
Reviewed-on: https://gem5-review.googlesource.com/7061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv')
-rw-r--r-- | src/arch/riscv/process.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc index 6fe935c13..b4fe1eefc 100644 --- a/src/arch/riscv/process.cc +++ b/src/arch/riscv/process.cc @@ -215,10 +215,10 @@ RiscvProcess::argsInit(int pageSize) RiscvISA::IntReg RiscvProcess::getSyscallArg(ThreadContext *tc, int &i) { - // RISC-V only has four system call argument registers by convention, so - // if a larger index is requested return 0 + // If a larger index is requested than there are syscall argument + // registers, return 0 RiscvISA::IntReg retval = 0; - if (i < 4) + if (i < SyscallArgumentRegs.size()) retval = tc->readIntReg(SyscallArgumentRegs[i]); i++; return retval; |