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author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 02:43:22 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 02:43:22 -0700 |
commit | 641513fe08f21d38b5aaf92638657ed3e2d37962 (patch) | |
tree | b20b2e8647057389de26f8b2e09fd043c1c46950 /src/arch/x86/apicregs.hh | |
parent | 9549694ecd1cc80e2b690631ea58d14778d368af (diff) | |
download | gem5-641513fe08f21d38b5aaf92638657ed3e2d37962.tar.xz |
X86: Start implementing the interrupt command register in the local APIC.
Diffstat (limited to 'src/arch/x86/apicregs.hh')
-rw-r--r-- | src/arch/x86/apicregs.hh | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/arch/x86/apicregs.hh b/src/arch/x86/apicregs.hh index 464c3af2d..dfea2650f 100644 --- a/src/arch/x86/apicregs.hh +++ b/src/arch/x86/apicregs.hh @@ -31,6 +31,8 @@ #ifndef __ARCH_X86_APICREGS_HH__ #define __ARCH_X86_APICREGS_HH__ +#include "base/bitunion.hh" + namespace X86ISA { enum ApicRegIndex @@ -86,6 +88,20 @@ namespace X86ISA { return (ApicRegIndex)(APIC_INTERRUPT_REQUEST_BASE + index); } + + BitUnion32(InterruptCommandRegLow) + Bitfield<7, 0> vector; + Bitfield<10, 8> deliveryMode; + Bitfield<11> destMode; + Bitfield<12> deliveryStatus; + Bitfield<14> level; + Bitfield<15> trigger; + Bitfield<19, 18> destShorthand; + EndBitUnion(InterruptCommandRegLow) + + BitUnion32(InterruptCommandRegHigh) + Bitfield<31, 24> destination; + EndBitUnion(InterruptCommandRegHigh) } #endif |