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author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-17 20:15:16 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-17 20:15:16 -0700 |
commit | cf2fc2613d7b80f72e886fb89ab7e347889994fd (patch) | |
tree | d699328e474ca4f4eb269329ea5549ba89ebf27f /src/arch/x86/isa/insts/simd128/integer | |
parent | c8a0cf5df735ad7f1ed0671d5e0c82bc62078d3d (diff) | |
download | gem5-cf2fc2613d7b80f72e886fb89ab7e347889994fd.tar.xz |
X86: Implement the media shifts that operate on 64 bits or less at a time.
Diffstat (limited to 'src/arch/x86/isa/insts/simd128/integer')
3 files changed, 183 insertions, 10 deletions
diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py index 18d6feb24..617033bc0 100644 --- a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py +++ b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py @@ -54,8 +54,73 @@ # Authors: Gabe Black microcode = ''' -# PSLLW -# PSLLD -# PSLLQ -# PSLLDQ +def macroop PSLLW_XMM_XMM { + msll xmmh, xmmh, xmmlm, size=2, ext=0 + msll xmml, xmml, xmmlm, size=2, ext=0 +}; + +def macroop PSLLW_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msll xmml, xmml, ufp1, size=2, ext=0 + msll xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSLLW_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msll xmml, xmml, ufp1, size=2, ext=0 + msll xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSLLW_XMM_I { + mslli xmml, xmml, imm, size=2, ext=0 + mslli xmmh, xmmh, imm, size=2, ext=0 +}; + +def macroop PSLLD_XMM_XMM { + msll xmmh, xmmh, xmmlm, size=4, ext=0 + msll xmml, xmml, xmmlm, size=4, ext=0 +}; + +def macroop PSLLD_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msll xmml, xmml, ufp1, size=4, ext=0 + msll xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSLLD_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msll xmml, xmml, ufp1, size=4, ext=0 + msll xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSLLD_XMM_I { + mslli xmml, xmml, imm, size=4, ext=0 + mslli xmmh, xmmh, imm, size=4, ext=0 +}; + +def macroop PSLLQ_XMM_XMM { + msll xmmh, xmmh, xmmlm, size=8, ext=0 + msll xmml, xmml, xmmlm, size=8, ext=0 +}; + +def macroop PSLLQ_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msll xmml, xmml, ufp1, size=8, ext=0 + msll xmmh, xmmh, ufp1, size=8, ext=0 +}; + +def macroop PSLLQ_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msll xmml, xmml, ufp1, size=8, ext=0 + msll xmmh, xmmh, ufp1, size=8, ext=0 +}; + +def macroop PSLLQ_XMM_I { + mslli xmml, xmml, imm, size=8, ext=0 + mslli xmmh, xmmh, imm, size=8, ext=0 +}; ''' +# PSLLDQ diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py index 63750e292..b88457a02 100644 --- a/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py +++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py @@ -54,6 +54,49 @@ # Authors: Gabe Black microcode = ''' -# PSRAW -# PSRAD +def macroop PSRAW_XMM_XMM { + msra xmmh, xmmh, xmmlm, size=2, ext=0 + msra xmml, xmml, xmmlm, size=2, ext=0 +}; + +def macroop PSRAW_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msra xmml, xmml, ufp1, size=2, ext=0 + msra xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSRAW_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msra xmml, xmml, ufp1, size=2, ext=0 + msra xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSRAW_XMM_I { + msrai xmml, xmml, imm, size=2, ext=0 + msrai xmmh, xmmh, imm, size=2, ext=0 +}; + +def macroop PSRAD_XMM_XMM { + msra xmmh, xmmh, xmmlm, size=4, ext=0 + msra xmml, xmml, xmmlm, size=4, ext=0 +}; + +def macroop PSRAD_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msra xmml, xmml, ufp1, size=4, ext=0 + msra xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSRAD_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msra xmml, xmml, ufp1, size=4, ext=0 + msra xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSRAD_XMM_I { + msrai xmml, xmml, imm, size=4, ext=0 + msrai xmmh, xmmh, imm, size=4, ext=0 +}; ''' diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py index fc6fb180b..c904eaf50 100644 --- a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py +++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py @@ -54,8 +54,73 @@ # Authors: Gabe Black microcode = ''' -# PSRLW -# PSRLD -# PSRLQ -# PSRLDQ +def macroop PSRLW_XMM_XMM { + msrl xmmh, xmmh, xmmlm, size=2, ext=0 + msrl xmml, xmml, xmmlm, size=2, ext=0 +}; + +def macroop PSRLW_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=2, ext=0 + msrl xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSRLW_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=2, ext=0 + msrl xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSRLW_XMM_I { + msrli xmml, xmml, imm, size=2, ext=0 + msrli xmmh, xmmh, imm, size=2, ext=0 +}; + +def macroop PSRLD_XMM_XMM { + msrl xmmh, xmmh, xmmlm, size=4, ext=0 + msrl xmml, xmml, xmmlm, size=4, ext=0 +}; + +def macroop PSRLD_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=4, ext=0 + msrl xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSRLD_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=4, ext=0 + msrl xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSRLD_XMM_I { + msrli xmml, xmml, imm, size=4, ext=0 + msrli xmmh, xmmh, imm, size=4, ext=0 +}; + +def macroop PSRLQ_XMM_XMM { + msrl xmmh, xmmh, xmmlm, size=8, ext=0 + msrl xmml, xmml, xmmlm, size=8, ext=0 +}; + +def macroop PSRLQ_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=8, ext=0 + msrl xmmh, xmmh, ufp1, size=8, ext=0 +}; + +def macroop PSRLQ_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=8, ext=0 + msrl xmmh, xmmh, ufp1, size=8, ext=0 +}; + +def macroop PSRLQ_XMM_I { + msrli xmml, xmml, imm, size=8, ext=0 + msrli xmmh, xmmh, imm, size=8, ext=0 +}; ''' +# PSRLDQ |