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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-08-13 13:36:37 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-08-13 13:36:37 -0700 |
| commit | e0043f8dbe926ed5bfadb504b0a69b1a1fbfcede (patch) | |
| tree | ca280844ff12304b869e955a94c9bd830047f70e /src/arch/x86/isa | |
| parent | 6bbd74e2d91cab8a1d5a2e340216722f3f249004 (diff) | |
| download | gem5-e0043f8dbe926ed5bfadb504b0a69b1a1fbfcede.tar.xz | |
O3: At the end of an instruction, force fetchAddr to something sensible.
It's possible (though until now very unlikely) for fetchAddr to get out of
sync with the actual PC of the current instruction. This change forcefull
resets fetchAddr at the end of every instruction.
Diffstat (limited to 'src/arch/x86/isa')
0 files changed, 0 insertions, 0 deletions