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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:50:25 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:50:25 -0400 |
| commit | d4e7c7edd35d1f5e6771077eeca83369c1169a33 (patch) | |
| tree | 6f452b3223faffa2ee4210b2cbb6412db2fb7bdb /src/arch/x86/miscregs.hh | |
| parent | fa7c81c6df5fdc1a17ffebbf431cb57ac84d79d0 (diff) | |
| download | gem5-d4e7c7edd35d1f5e6771077eeca83369c1169a33.tar.xz | |
X86: Keep handy values like the operating mode in one register.
Diffstat (limited to 'src/arch/x86/miscregs.hh')
| -rw-r--r-- | src/arch/x86/miscregs.hh | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh index 90f1d9fda..caa1e817b 100644 --- a/src/arch/x86/miscregs.hh +++ b/src/arch/x86/miscregs.hh @@ -130,6 +130,9 @@ namespace X86ISA // Flags register MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, + //Register to keep handy values like the CPU mode in. + MISCREG_M5_REG, + /* * Model Specific Registers */ @@ -563,6 +566,12 @@ namespace X86ISA Bitfield<0> cf; // Carry Flag EndBitUnion(RFLAGS) + BitUnion64(HandyM5Reg) + Bitfield<0> mode; + Bitfield<3, 1> submode; + Bitfield<5, 4> cpl; + EndBitUnion(HandyM5Reg) + /** * Control registers */ |