gpu-compute: Wavefront refactoring

Renaming members of the Wavefront class in accordance with the style guide.

5 files changed, 111 insertions, 111 deletions

diff --git a/src/arch/hsail/gen.py b/src/arch/hsail/gen.py
index f77680541..22832658f 100755
--- a/src/arch/hsail/gen.py
+++ b/src/arch/hsail/gen.py
@@ -233,7 +233,7 @@ $class_name::execute(GPUDynInstPtr gpuDynInst)
 
     typedef Base::DestCType DestCType;
 
-    const VectorMask &mask = w->get_pred();
+    const VectorMask &mask = w->getPred();
 
     for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
         if (mask[lane]) {
@@ -254,7 +254,7 @@ $class_name::execute(GPUDynInstPtr gpuDynInst)
     typedef Base::DestCType DestCType;
     typedef Base::SrcCType  SrcCType;
 
-    const VectorMask &mask = w->get_pred();
+    const VectorMask &mask = w->getPred();
 
     for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
         if (mask[lane]) {
@@ -275,7 +275,7 @@ $class_name<DataType>::execute(GPUDynInstPtr gpuDynInst)
 {
     Wavefront *w = gpuDynInst->wavefront();
 
-    const VectorMask &mask = w->get_pred();
+    const VectorMask &mask = w->getPred();
 
     for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
         if (mask[lane]) {
@@ -310,7 +310,7 @@ $class_name<DataType>::execute(GPUDynInstPtr gpuDynInst)
     typedef typename Base::Src1CType Src1T;
     typedef typename Base::Src2CType Src2T;
 
-    const VectorMask &mask = w->get_pred();
+    const VectorMask &mask = w->getPred();
 
     for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
         if (mask[lane]) {
@@ -344,7 +344,7 @@ $class_name<DataType>::execute(GPUDynInstPtr gpuDynInst)
     typedef CType Src0T;
     typedef typename Base::Src1CType Src1T;
 
-    const VectorMask &mask = w->get_pred();
+    const VectorMask &mask = w->getPred();
 
     for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
         if (mask[lane]) {
@@ -371,7 +371,7 @@ $class_name<DataType>::execute(GPUDynInstPtr gpuDynInst)
 {
     Wavefront *w = gpuDynInst->wavefront();
 
-    const VectorMask &mask = w->get_pred();
+    const VectorMask &mask = w->getPred();
     for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
         if (mask[lane]) {
             CType dest_val;
@@ -399,7 +399,7 @@ $class_name<DestDataType, SrcDataType>::execute(GPUDynInstPtr gpuDynInst)
 {
     Wavefront *w = gpuDynInst->wavefront();
 
-    const VectorMask &mask = w->get_pred();
+    const VectorMask &mask = w->getPred();
 
     for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
         if (mask[lane]) {
@@ -745,17 +745,17 @@ def gen_special(brig_opcode, expr, dest_type='U32'):
 
     gen(brig_opcode, None, expr, base_class)
 
-gen_special('WorkItemId', 'w->workitemid[src0][lane]')
+gen_special('WorkItemId', 'w->workItemId[src0][lane]')
 gen_special('WorkItemAbsId',
-    'w->workitemid[src0][lane] + (w->workgroupid[src0] * w->workgroupsz[src0])')
-gen_special('WorkGroupId', 'w->workgroupid[src0]')
-gen_special('WorkGroupSize', 'w->workgroupsz[src0]')
-gen_special('CurrentWorkGroupSize', 'w->workgroupsz[src0]')
-gen_special('GridSize', 'w->gridsz[src0]')
+    'w->workItemId[src0][lane] + (w->workGroupId[src0] * w->workGroupSz[src0])')
+gen_special('WorkGroupId', 'w->workGroupId[src0]')
+gen_special('WorkGroupSize', 'w->workGroupSz[src0]')
+gen_special('CurrentWorkGroupSize', 'w->workGroupSz[src0]')
+gen_special('GridSize', 'w->gridSz[src0]')
 gen_special('GridGroups',
-    'divCeil(w->gridsz[src0],w->workgroupsz[src0])')
+    'divCeil(w->gridSz[src0],w->workGroupSz[src0])')
 gen_special('LaneId', 'lane')
-gen_special('WaveId', 'w->dynwaveid')
+gen_special('WaveId', 'w->dynWaveId')
 gen_special('Clock', 'w->computeUnit->shader->tick_cnt', 'U64')
 
 # gen_special('CU'', ')
diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh
index 90609c365..48e022ff7 100644
--- a/src/arch/hsail/insts/decl.hh
+++ b/src/arch/hsail/insts/decl.hh
@@ -960,7 +960,7 @@ namespace HsailISA
                 gpuDynInst->simdId = w->simdId;
                 gpuDynInst->wfSlotId = w->wfSlotId;
                 gpuDynInst->wfDynId = w->wfDynId;
-                gpuDynInst->kern_id = w->kern_id;
+                gpuDynInst->kern_id = w->kernId;
                 gpuDynInst->cu_id = w->computeUnit->cu_id;
 
                 gpuDynInst->memoryOrder =
@@ -971,10 +971,10 @@ namespace HsailISA
                 GlobalMemPipeline* gmp = &(w->computeUnit->globalMemoryPipe);
                 gmp->getGMReqFIFO().push(gpuDynInst);
 
-                w->wr_gm_reqs_in_pipe--;
-                w->rd_gm_reqs_in_pipe--;
-                w->mem_reqs_in_pipe--;
-                w->outstanding_reqs++;
+                w->wrGmReqsInPipe--;
+                w->rdGmReqsInPipe--;
+                w->memReqsInPipe--;
+                w->outstandingReqs++;
             } else if (o_type == Enums::OT_SHARED_MEMFENCE) {
                 // no-op
             } else {
diff --git a/src/arch/hsail/insts/main.cc b/src/arch/hsail/insts/main.cc
index 004054524..f1662430a 100644
--- a/src/arch/hsail/insts/main.cc
+++ b/src/arch/hsail/insts/main.cc
@@ -131,12 +131,12 @@ namespace HsailISA
     {
         Wavefront *w = gpuDynInst->wavefront();
 
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
 
         // mask off completed work-items
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
             if (mask[lane]) {
-                w->init_mask[lane] = 0;
+                w->initMask[lane] = 0;
             }
 
         }
@@ -149,14 +149,14 @@ namespace HsailISA
         }
 
         // if all work-items have completed, then wave-front is done
-        if (w->init_mask.none()) {
+        if (w->initMask.none()) {
             w->status = Wavefront::S_STOPPED;
 
             int32_t refCount = w->computeUnit->getLds().
-                                   decreaseRefCounter(w->dispatchid, w->wg_id);
+                                   decreaseRefCounter(w->dispatchId, w->wgId);
 
             DPRINTF(GPUExec, "CU%d: decrease ref ctr WG[%d] to [%d]\n",
-                            w->computeUnit->cu_id, w->wg_id, refCount);
+                            w->computeUnit->cu_id, w->wgId, refCount);
 
             // free the vector registers of the completed wavefront
             w->computeUnit->vectorRegsReserved[w->simdId] -=
@@ -201,8 +201,8 @@ namespace HsailISA
     {
         Wavefront *w = gpuDynInst->wavefront();
 
-        assert(w->barrier_cnt == w->old_barrier_cnt);
-        w->barrier_cnt = w->old_barrier_cnt + 1;
+        assert(w->barrierCnt == w->oldBarrierCnt);
+        w->barrierCnt = w->oldBarrierCnt + 1;
         w->stalledAtBarrier = true;
     }
 } // namespace HsailISA
diff --git a/src/arch/hsail/insts/mem_impl.hh b/src/arch/hsail/insts/mem_impl.hh
index 8329c6e8a..3042e2201 100644
--- a/src/arch/hsail/insts/mem_impl.hh
+++ b/src/arch/hsail/insts/mem_impl.hh
@@ -59,7 +59,7 @@ namespace HsailISA
         Wavefront *w = gpuDynInst->wavefront();
 
         typedef typename DestDataType::CType CType M5_VAR_USED;
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         std::vector<Addr> addr_vec;
         addr_vec.resize(w->computeUnit->wfSize(), (Addr)0);
         this->addr.calcVector(w, addr_vec);
@@ -159,7 +159,7 @@ namespace HsailISA
         Wavefront *w = gpuDynInst->wavefront();
 
         typedef typename MemDataType::CType MemCType;
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
 
         // Kernarg references are handled uniquely for now (no Memory Request
         // is used), so special-case them up front.  Someday we should
@@ -230,7 +230,7 @@ namespace HsailISA
         m->simdId = w->simdId;
         m->wfSlotId = w->wfSlotId;
         m->wfDynId = w->wfDynId;
-        m->kern_id = w->kern_id;
+        m->kern_id = w->kernId;
         m->cu_id = w->computeUnit->cu_id;
         m->latency.init(&w->computeUnit->shader->tick_cnt);
 
@@ -261,8 +261,8 @@ namespace HsailISA
             }
 
             w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-            w->outstanding_reqs_rd_gm++;
-            w->rd_gm_reqs_in_pipe--;
+            w->outstandingReqsRdGm++;
+            w->rdGmReqsInPipe--;
             break;
 
           case Brig::BRIG_SEGMENT_SPILL:
@@ -281,14 +281,14 @@ namespace HsailISA
                         m->addr[lane] = m->addr[lane] * w->spillWidth +
                                         lane * sizeof(MemCType) + w->spillBase;
 
-                        w->last_addr[lane] = m->addr[lane];
+                        w->lastAddr[lane] = m->addr[lane];
                     }
                 }
             }
 
             w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-            w->outstanding_reqs_rd_gm++;
-            w->rd_gm_reqs_in_pipe--;
+            w->outstandingReqsRdGm++;
+            w->rdGmReqsInPipe--;
             break;
 
           case Brig::BRIG_SEGMENT_GROUP:
@@ -296,8 +296,8 @@ namespace HsailISA
             m->pipeId = LDSMEM_PIPE;
             m->latency.set(w->computeUnit->shader->ticks(24));
             w->computeUnit->localMemoryPipe.getLMReqFIFO().push(m);
-            w->outstanding_reqs_rd_lm++;
-            w->rd_lm_reqs_in_pipe--;
+            w->outstandingReqsRdLm++;
+            w->rdLmReqsInPipe--;
             break;
 
           case Brig::BRIG_SEGMENT_READONLY:
@@ -313,8 +313,8 @@ namespace HsailISA
             }
 
             w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-            w->outstanding_reqs_rd_gm++;
-            w->rd_gm_reqs_in_pipe--;
+            w->outstandingReqsRdGm++;
+            w->rdGmReqsInPipe--;
             break;
 
           case Brig::BRIG_SEGMENT_PRIVATE:
@@ -332,8 +332,8 @@ namespace HsailISA
                 }
             }
             w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-            w->outstanding_reqs_rd_gm++;
-            w->rd_gm_reqs_in_pipe--;
+            w->outstandingReqsRdGm++;
+            w->rdGmReqsInPipe--;
             break;
 
           default:
@@ -341,8 +341,8 @@ namespace HsailISA
                   m->addr[0]);
         }
 
-        w->outstanding_reqs++;
-        w->mem_reqs_in_pipe--;
+        w->outstandingReqs++;
+        w->memReqsInPipe--;
     }
 
     template<typename OperationType, typename SrcDataType,
@@ -355,7 +355,7 @@ namespace HsailISA
 
         typedef typename OperationType::CType CType;
 
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
 
         // arg references are handled uniquely for now (no Memory Request
         // is used), so special-case them up front.  Someday we should
@@ -419,7 +419,7 @@ namespace HsailISA
         m->simdId = w->simdId;
         m->wfSlotId = w->wfSlotId;
         m->wfDynId = w->wfDynId;
-        m->kern_id = w->kern_id;
+        m->kern_id = w->kernId;
         m->cu_id = w->computeUnit->cu_id;
         m->latency.init(&w->computeUnit->shader->tick_cnt);
 
@@ -448,8 +448,8 @@ namespace HsailISA
             }
 
             w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-            w->outstanding_reqs_wr_gm++;
-            w->wr_gm_reqs_in_pipe--;
+            w->outstandingReqsWrGm++;
+            w->wrGmReqsInPipe--;
             break;
 
           case Brig::BRIG_SEGMENT_SPILL:
@@ -469,8 +469,8 @@ namespace HsailISA
             }
 
             w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-            w->outstanding_reqs_wr_gm++;
-            w->wr_gm_reqs_in_pipe--;
+            w->outstandingReqsWrGm++;
+            w->wrGmReqsInPipe--;
             break;
 
           case Brig::BRIG_SEGMENT_GROUP:
@@ -478,8 +478,8 @@ namespace HsailISA
             m->pipeId = LDSMEM_PIPE;
             m->latency.set(w->computeUnit->shader->ticks(24));
             w->computeUnit->localMemoryPipe.getLMReqFIFO().push(m);
-            w->outstanding_reqs_wr_lm++;
-            w->wr_lm_reqs_in_pipe--;
+            w->outstandingReqsWrLm++;
+            w->wrLmReqsInPipe--;
             break;
 
           case Brig::BRIG_SEGMENT_PRIVATE:
@@ -497,16 +497,16 @@ namespace HsailISA
             }
 
             w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-            w->outstanding_reqs_wr_gm++;
-            w->wr_gm_reqs_in_pipe--;
+            w->outstandingReqsWrGm++;
+            w->wrGmReqsInPipe--;
             break;
 
           default:
             fatal("Store to unsupported segment %d\n", this->segment);
         }
 
-        w->outstanding_reqs++;
-        w->mem_reqs_in_pipe--;
+        w->outstandingReqs++;
+        w->memReqsInPipe--;
     }
 
     template<typename OperationType, typename SrcDataType,
@@ -596,7 +596,7 @@ namespace HsailISA
         m->simdId = w->simdId;
         m->wfSlotId = w->wfSlotId;
         m->wfDynId = w->wfDynId;
-        m->kern_id = w->kern_id;
+        m->kern_id = w->kernId;
         m->cu_id = w->computeUnit->cu_id;
         m->latency.init(&w->computeUnit->shader->tick_cnt);
 
@@ -607,10 +607,10 @@ namespace HsailISA
             m->pipeId = GLBMEM_PIPE;
 
             w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-            w->outstanding_reqs_wr_gm++;
-            w->wr_gm_reqs_in_pipe--;
-            w->outstanding_reqs_rd_gm++;
-            w->rd_gm_reqs_in_pipe--;
+            w->outstandingReqsWrGm++;
+            w->wrGmReqsInPipe--;
+            w->outstandingReqsRdGm++;
+            w->rdGmReqsInPipe--;
             break;
 
           case Brig::BRIG_SEGMENT_GROUP:
@@ -618,10 +618,10 @@ namespace HsailISA
             m->pipeId = LDSMEM_PIPE;
             m->latency.set(w->computeUnit->shader->ticks(24));
             w->computeUnit->localMemoryPipe.getLMReqFIFO().push(m);
-            w->outstanding_reqs_wr_lm++;
-            w->wr_lm_reqs_in_pipe--;
-            w->outstanding_reqs_rd_lm++;
-            w->rd_lm_reqs_in_pipe--;
+            w->outstandingReqsWrLm++;
+            w->wrLmReqsInPipe--;
+            w->outstandingReqsRdLm++;
+            w->rdLmReqsInPipe--;
             break;
 
           default:
@@ -629,8 +629,8 @@ namespace HsailISA
                   this->segment);
         }
 
-        w->outstanding_reqs++;
-        w->mem_reqs_in_pipe--;
+        w->outstandingReqs++;
+        w->memReqsInPipe--;
     }
 
     const char* atomicOpToString(Brig::BrigAtomicOperation atomicOp);
diff --git a/src/arch/hsail/insts/pseudo_inst.cc b/src/arch/hsail/insts/pseudo_inst.cc
index 56ca8047c..2bfc5aaad 100644
--- a/src/arch/hsail/insts/pseudo_inst.cc
+++ b/src/arch/hsail/insts/pseudo_inst.cc
@@ -79,7 +79,7 @@ namespace HsailISA
     void
     Call::execPseudoInst(Wavefront *w, GPUDynInstPtr gpuDynInst)
     {
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
 
         int op = 0;
         bool got_op = false;
@@ -181,7 +181,7 @@ namespace HsailISA
     Call::MagicPrintLane(Wavefront *w)
     {
     #if TRACING_ON
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
             if (mask[lane]) {
                 int src_val1 = src1.get<int>(w, lane, 1);
@@ -204,7 +204,7 @@ namespace HsailISA
     Call::MagicPrintLane64(Wavefront *w)
     {
     #if TRACING_ON
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
             if (mask[lane]) {
                 int64_t src_val1 = src1.get<int64_t>(w, lane, 1);
@@ -227,7 +227,7 @@ namespace HsailISA
     Call::MagicPrintWF32(Wavefront *w)
     {
     #if TRACING_ON
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         std::string res_str;
         res_str = csprintf("krl_prt (%s)\n", disassemble());
 
@@ -265,7 +265,7 @@ namespace HsailISA
     Call::MagicPrintWF32ID(Wavefront *w)
     {
     #if TRACING_ON
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         std::string res_str;
         int src_val3 = -1;
         res_str = csprintf("krl_prt (%s)\n", disassemble());
@@ -307,7 +307,7 @@ namespace HsailISA
     Call::MagicPrintWF64(Wavefront *w)
     {
     #if TRACING_ON
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         std::string res_str;
         res_str = csprintf("krl_prt (%s)\n", disassemble());
 
@@ -345,7 +345,7 @@ namespace HsailISA
     Call::MagicPrintWFID64(Wavefront *w)
     {
     #if TRACING_ON
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         std::string res_str;
         int src_val3 = -1;
         res_str = csprintf("krl_prt (%s)\n", disassemble());
@@ -387,7 +387,7 @@ namespace HsailISA
     Call::MagicPrintWFFloat(Wavefront *w)
     {
     #if TRACING_ON
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         std::string res_str;
         res_str = csprintf("krl_prt (%s)\n", disassemble());
 
@@ -425,7 +425,7 @@ namespace HsailISA
         res_str = csprintf("Breakpoint encountered for wavefront %i\n",
                            w->wfSlotId);
 
-        res_str += csprintf("  Kern ID: %i\n", w->kern_id);
+        res_str += csprintf("  Kern ID: %i\n", w->kernId);
         res_str += csprintf("  Phase ID: %i\n", w->simdId);
         res_str += csprintf("  Executing on CU #%i\n", w->computeUnit->cu_id);
         res_str += csprintf("  Exec mask: ");
@@ -455,7 +455,7 @@ namespace HsailISA
     void
     Call::MagicPrefixSum(Wavefront *w)
     {
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         int res = 0;
 
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
@@ -474,7 +474,7 @@ namespace HsailISA
         //   The reduction instruction takes up to 64 inputs (one from
         //   each thread in a WF) and sums them. It returns the sum to
         //   each thread in the WF.
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         int res = 0;
 
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
@@ -494,7 +494,7 @@ namespace HsailISA
     void
     Call::MagicMaskLower(Wavefront *w)
     {
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         int res = 0;
 
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
@@ -519,7 +519,7 @@ namespace HsailISA
     void
     Call::MagicMaskUpper(Wavefront *w)
     {
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         int res = 0;
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
             if (mask[lane]) {
@@ -544,42 +544,42 @@ namespace HsailISA
     void
     Call::MagicJoinWFBar(Wavefront *w)
     {
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         int max_cnt = 0;
 
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
             if (mask[lane]) {
-                w->bar_cnt[lane]++;
+                w->barCnt[lane]++;
 
-                if (w->bar_cnt[lane] > max_cnt) {
-                    max_cnt = w->bar_cnt[lane];
+                if (w->barCnt[lane] > max_cnt) {
+                    max_cnt = w->barCnt[lane];
                 }
             }
         }
 
-        if (max_cnt > w->max_bar_cnt) {
-            w->max_bar_cnt = max_cnt;
+        if (max_cnt > w->maxBarCnt) {
+            w->maxBarCnt = max_cnt;
         }
     }
 
     void
     Call::MagicWaitWFBar(Wavefront *w)
     {
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         int max_cnt = 0;
 
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
             if (mask[lane]) {
-                w->bar_cnt[lane]--;
+                w->barCnt[lane]--;
             }
 
-            if (w->bar_cnt[lane] > max_cnt) {
-                max_cnt = w->bar_cnt[lane];
+            if (w->barCnt[lane] > max_cnt) {
+                max_cnt = w->barCnt[lane];
             }
         }
 
-        if (max_cnt < w->max_bar_cnt) {
-            w->max_bar_cnt = max_cnt;
+        if (max_cnt < w->maxBarCnt) {
+            w->maxBarCnt = max_cnt;
         }
 
         w->instructionBuffer.erase(w->instructionBuffer.begin() + 1,
@@ -591,7 +591,7 @@ namespace HsailISA
     void
     Call::MagicPanic(Wavefront *w)
     {
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
 
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
             if (mask[lane]) {
@@ -648,12 +648,12 @@ namespace HsailISA
         m->pipeId = GLBMEM_PIPE;
         m->latency.set(w->computeUnit->shader->ticks(64));
         w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-        w->outstanding_reqs_wr_gm++;
-        w->wr_gm_reqs_in_pipe--;
-        w->outstanding_reqs_rd_gm++;
-        w->rd_gm_reqs_in_pipe--;
-        w->outstanding_reqs++;
-        w->mem_reqs_in_pipe--;
+        w->outstandingReqsWrGm++;
+        w->wrGmReqsInPipe--;
+        w->outstandingReqsRdGm++;
+        w->rdGmReqsInPipe--;
+        w->outstandingReqs++;
+        w->memReqsInPipe--;
     }
 
     void
@@ -687,12 +687,12 @@ namespace HsailISA
         m->pipeId = GLBMEM_PIPE;
         m->latency.set(w->computeUnit->shader->ticks(64));
         w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-        w->outstanding_reqs_wr_gm++;
-        w->wr_gm_reqs_in_pipe--;
-        w->outstanding_reqs_rd_gm++;
-        w->rd_gm_reqs_in_pipe--;
-        w->outstanding_reqs++;
-        w->mem_reqs_in_pipe--;
+        w->outstandingReqsWrGm++;
+        w->wrGmReqsInPipe--;
+        w->outstandingReqsRdGm++;
+        w->rdGmReqsInPipe--;
+        w->outstandingReqs++;
+        w->memReqsInPipe--;
     }
 
     void
@@ -725,16 +725,16 @@ namespace HsailISA
         m->pipeId = GLBMEM_PIPE;
         m->latency.set(w->computeUnit->shader->ticks(1));
         w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
-        w->outstanding_reqs_rd_gm++;
-        w->rd_gm_reqs_in_pipe--;
-        w->outstanding_reqs++;
-        w->mem_reqs_in_pipe--;
+        w->outstandingReqsRdGm++;
+        w->rdGmReqsInPipe--;
+        w->outstandingReqs++;
+        w->memReqsInPipe--;
     }
 
     void
     Call::MagicXactCasLd(Wavefront *w)
     {
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         int src_val1 = 0;
 
         for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
@@ -756,7 +756,7 @@ namespace HsailISA
     void
     Call::MagicMostSigThread(Wavefront *w)
     {
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         unsigned mst = true;
 
         for (int lane = w->computeUnit->wfSize() - 1; lane >= 0; --lane) {
@@ -770,7 +770,7 @@ namespace HsailISA
     void
     Call::MagicMostSigBroadcast(Wavefront *w)
     {
-        const VectorMask &mask = w->get_pred();
+        const VectorMask &mask = w->getPred();
         int res = 0;
         bool got_res = false;