summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2009-08-05 03:02:05 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-08-05 03:02:05 -0700
commit3990445354914ffc3a56ceb93b1fde222d7236c6 (patch)
tree36e3528d5ecfee00b785990d590289daed252961 /src/arch
parentd265f7683e761207a60d9187324846aedf674c84 (diff)
downloadgem5-3990445354914ffc3a56ceb93b1fde222d7236c6.tar.xz
X86: Set the flags on rotate left with carry instructions.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py
index baefc0e11..3be954768 100644
--- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py
+++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py
@@ -176,13 +176,13 @@ def macroop ROR_P_R
def macroop RCL_R_I
{
- rcli reg, reg, imm
+ rcli reg, reg, imm, flags=(OF,CF)
};
def macroop RCL_M_I
{
ldst t1, seg, sib, disp
- rcli t1, t1, imm
+ rcli t1, t1, imm, flags=(OF,CF)
st t1, seg, sib, disp
};
@@ -190,19 +190,19 @@ def macroop RCL_P_I
{
rdip t7
ldst t1, seg, riprel, disp
- rcli t1, t1, imm
+ rcli t1, t1, imm, flags=(OF,CF)
st t1, seg, riprel, disp
};
def macroop RCL_1_R
{
- rcli reg, reg, 1
+ rcli reg, reg, 1, flags=(OF,CF)
};
def macroop RCL_1_M
{
ldst t1, seg, sib, disp
- rcli t1, t1, 1
+ rcli t1, t1, 1, flags=(OF,CF)
st t1, seg, sib, disp
};
@@ -210,19 +210,19 @@ def macroop RCL_1_P
{
rdip t7
ldst t1, seg, riprel, disp
- rcli t1, t1, 1
+ rcli t1, t1, 1, flags=(OF,CF)
st t1, seg, riprel, disp
};
def macroop RCL_R_R
{
- rcl reg, reg, regm
+ rcl reg, reg, regm, flags=(OF,CF)
};
def macroop RCL_M_R
{
ldst t1, seg, sib, disp
- rcl t1, t1, reg
+ rcl t1, t1, reg, flags=(OF,CF)
st t1, seg, sib, disp
};
@@ -230,7 +230,7 @@ def macroop RCL_P_R
{
rdip t7
ldst t1, seg, riprel, disp
- rcl t1, t1, reg
+ rcl t1, t1, reg, flags=(OF,CF)
st t1, seg, riprel, disp
};