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author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:48 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:48 -0500 |
commit | e09e9fa279dec86b171b5e3efeb7057fa0d21cc9 (patch) | |
tree | 81fe4595ffa298f566a595caa54d5166c9bc09af /src/cpu/BaseCPU.py | |
parent | 964aa49d1523787c06491453a85fad511b0a5883 (diff) | |
download | gem5-e09e9fa279dec86b171b5e3efeb7057fa0d21cc9.tar.xz |
cpu: Flush TLBs on switchOut()
This changeset inserts a TLB flush in BaseCPU::switchOut to prevent
stale translations when doing repeated switching. Additionally, the
TLB flushing functionality is exported to the Python to make debugging
of switching/checkpointing easier.
A simulation script will typically use the TLB flushing functionality
to generate a reference trace. The following sequence can be used to
simulate a handover (this depends on how drain is implemented, but is
generally the case) between identically configured CPU models:
m5.drain(test_sys)
[ cpu.flushTLBs() for cpu in test_sys.cpu ]
m5.resume(test_sys)
The generated trace should normally be identical to a trace generated
when switching between identically configured CPU models or
checkpointing and resuming.
Diffstat (limited to 'src/cpu/BaseCPU.py')
-rw-r--r-- | src/cpu/BaseCPU.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6673b9d41..900a23991 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -96,6 +96,7 @@ class BaseCPU(MemObject): void switchOut(); void takeOverFrom(BaseCPU *cpu); bool switchedOut(); + void flushTLBs(); ''') def takeOverFrom(self, old_cpu): |