diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-08-01 22:50:14 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-08-01 22:50:14 -0700 |
commit | a13a706a207296b40dbe43576fad423cf5f4679a (patch) | |
tree | 119bd1bd09542130d603c8f30c0494313180753a /src/cpu/base_dyn_inst.hh | |
parent | 1c2800465480993040e3058ef94ce30efbe982ec (diff) | |
download | gem5-a13a706a207296b40dbe43576fad423cf5f4679a.tar.xz |
Fix setting of INST_FETCH flag for O3 CPU.
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
-rw-r--r-- | src/cpu/base_dyn_inst.hh | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index c6e57b612..f4ff88209 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -857,9 +857,8 @@ inline Fault BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) { reqMade = true; - Request *req = new Request(); - req->setVirt(asid, addr, sizeof(T), flags, this->PC); - req->setThreadContext(thread->contextId(), threadNumber); + Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, + thread->contextId(), threadNumber); fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read); @@ -913,9 +912,8 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) } reqMade = true; - Request *req = new Request(); - req->setVirt(asid, addr, sizeof(T), flags, this->PC); - req->setThreadContext(thread->contextId(), threadNumber); + Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, + thread->contextId(), threadNumber); fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); |