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| author | Gabe Black <gabeblack@google.com> | 2018-10-18 17:34:08 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-22 21:15:45 +0000 |
| commit | 230b892fa3f484a46f4cd77f889f8793416b91e2 (patch) | |
| tree | 53b32ed7120d019399e36d04655487745bbba9ee /src/cpu/checker/cpu.hh | |
| parent | 774770a6410abb129e2a19de1ca50d7c0c311fef (diff) | |
| download | gem5-230b892fa3f484a46f4cd77f889f8793416b91e2.tar.xz | |
arch: cpu: Stop passing around misc registers by reference.
These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.
Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/checker/cpu.hh')
| -rw-r--r-- | src/cpu/checker/cpu.hh | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 2c7e022bd..4468689bd 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -417,7 +417,7 @@ class CheckerCPU : public BaseCPU, public ExecContext } void - setMiscRegNoEffect(int misc_reg, const RegVal &val) + setMiscRegNoEffect(int misc_reg, RegVal val) { DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); @@ -426,7 +426,7 @@ class CheckerCPU : public BaseCPU, public ExecContext } void - setMiscReg(int misc_reg, const RegVal &val) override + setMiscReg(int misc_reg, RegVal val) override { DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); @@ -443,8 +443,7 @@ class CheckerCPU : public BaseCPU, public ExecContext } void - setMiscRegOperand(const StaticInst *si, int idx, - const RegVal &val) override + setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isMiscReg()); |