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author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-22 11:16:40 -0800 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-22 11:16:40 -0800 |
commit | 63a25a56ccc93c24703fec87f830c833974e7060 (patch) | |
tree | a0f12244a32eb7da2963ca974ab49a993aee2cfc /src/cpu/inorder/resources/tlb_unit.hh | |
parent | 8ea71c3907a411de9c203b45bfd6eab24e3ad849 (diff) | |
parent | 77eed184f529c4ccbef59ad2018d18ff3fbb54af (diff) | |
download | gem5-63a25a56ccc93c24703fec87f830c833974e7060.tar.xz |
m5: merged in hammer fix
Diffstat (limited to 'src/cpu/inorder/resources/tlb_unit.hh')
-rw-r--r-- | src/cpu/inorder/resources/tlb_unit.hh | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh index eb1bf55f0..904ac3eba 100644 --- a/src/cpu/inorder/resources/tlb_unit.hh +++ b/src/cpu/inorder/resources/tlb_unit.hh @@ -99,9 +99,15 @@ class TLBUnitRequest : public ResourceRequest { typedef ThePipeline::DynInstPtr DynInstPtr; public: - TLBUnitRequest(TLBUnit *res, DynInstPtr inst, int stage_num, int res_idx, int slot_num, - unsigned _cmd) - : ResourceRequest(res, inst, stage_num, res_idx, slot_num, _cmd) + TLBUnitRequest(TLBUnit *res) + : ResourceRequest(res), memReq(NULL) + { + } + + RequestPtr memReq; + + void setRequest(DynInstPtr inst, int stage_num, int res_idx, int slot_num, + unsigned _cmd) { Addr aligned_addr; int req_size; @@ -131,9 +137,10 @@ class TLBUnitRequest : public ResourceRequest { inst->readTid()); memReq = inst->dataMemReq; } + + ResourceRequest::setRequest(inst, stage_num, res_idx, slot_num, _cmd); } - RequestPtr memReq; }; |