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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-20 17:18:35 -0400 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-20 17:18:35 -0400 |
commit | e1403fc2af61c224c573c47c77a36f9b1b78e7df (patch) | |
tree | 07647bb8697ac256d180bf8de35080eee2a63f3e /src/cpu/minor/cpu.hh | |
parent | 2b0438a11eb6a9640b06da91e8a300d0ac3ad81a (diff) | |
download | gem5-e1403fc2af61c224c573c47c77a36f9b1b78e7df.tar.xz |
alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
activate(), suspend(), and halt() used on thread contexts had an optional
delay parameter. However this parameter was often ignored. Also, when used,
the delay was seemily arbitrarily set to 0 or 1 cycle (no other delays were
ever specified). This patch removes the delay parameter and 'Events'
associated with them across all ISAs and cores. Unused activate logic
is also removed.
Diffstat (limited to 'src/cpu/minor/cpu.hh')
-rw-r--r-- | src/cpu/minor/cpu.hh | 19 |
1 files changed, 1 insertions, 18 deletions
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh index 80f41b5d2..507261fbd 100644 --- a/src/cpu/minor/cpu.hh +++ b/src/cpu/minor/cpu.hh @@ -78,23 +78,6 @@ typedef SimpleThread MinorThread; class MinorCPU : public BaseCPU { protected: - /** Event for delayed wakeup of a thread */ - class ThreadActivateEvent : public Event - { - public: - MinorCPU &cpu; - ThreadID thread_id; - - ThreadActivateEvent(MinorCPU &cpu_, ThreadID thread_id_) : - cpu(cpu_), thread_id(thread_id_) - { } - - void process(); - }; - - /** Events to wakeup each thread */ - std::vector<ThreadActivateEvent *> threadActivateEvents; - /** pipeline is a container for the clockable pipeline stage objects. * Elements of pipeline call TheISA to implement the model. */ Minor::Pipeline *pipeline; @@ -184,7 +167,7 @@ class MinorCPU : public BaseCPU void takeOverFrom(BaseCPU *old_cpu); /** Thread activation interface from BaseCPU. */ - void activateContext(ThreadID thread_id, Cycles delay); + void activateContext(ThreadID thread_id); void suspendContext(ThreadID thread_id); /** Interface for stages to signal that they have become active after |