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author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-12-07 16:19:57 -0800 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-12-07 16:19:57 -0800 |
commit | e681c0f7b30f521805ebec04271435306f4c56ed (patch) | |
tree | 4b060d7175b0d90c9d4a731d0cad304b60dac029 /src/cpu/o3/commit.hh | |
parent | 719f9a6d4fba16af38dcfd62b25a4d708156699f (diff) | |
download | gem5-e681c0f7b30f521805ebec04271435306f4c56ed.tar.xz |
O3: Support squashing all state after special instruction
For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply
marking the instruction as Serializing isn't enough beacuse that only
stops rename. This provides a mechanism to squash all the instructions
and refetch them
Diffstat (limited to 'src/cpu/o3/commit.hh')
-rw-r--r-- | src/cpu/o3/commit.hh | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 326f3a1d3..468153dc7 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -245,6 +245,13 @@ class DefaultCommit /** Handles squashing due to an TC write. */ void squashFromTC(ThreadID tid); + /** Handles squashing from instruction with SquashAfter set. + * This differs from the other squashes as it squashes following + * instructions instead of the current instruction and doesn't + * clean up various status bits about traps/tc writes pending. + */ + void squashAfter(ThreadID tid, uint64_t squash_after_seq_num); + #if FULL_SYSTEM /** Handles processing an interrupt. */ void handleInterrupt(); |