diff options
author | Anthony Gutierrez <atgutier@umich.edu> | 2012-08-15 10:38:08 -0400 |
---|---|---|
committer | Anthony Gutierrez <atgutier@umich.edu> | 2012-08-15 10:38:08 -0400 |
commit | 0b3897fc90901953e9d016466c37ab507f85023c (patch) | |
tree | 0e8b1fec8d7c4871686903d573e9fd0fd8734d1e /src/cpu/o3/cpu.cc | |
parent | 5a648f2074caad8aee97e03f27e8eecc527a2cba (diff) | |
download | gem5-0b3897fc90901953e9d016466c37ab507f85023c.tar.xz |
O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.
This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r-- | src/cpu/o3/cpu.cc | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index e8fc968b7..64c54e26a 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -55,6 +55,7 @@ #include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" #include "debug/Activity.hh" +#include "debug/Drain.hh" #include "debug/O3CPU.hh" #include "debug/Quiesce.hh" #include "enums/MemoryMode.hh" @@ -260,7 +261,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) if (!deferRegistration) { _status = Running; } else { - _status = Idle; + _status = SwitchedOut; } if (params->checker) { @@ -1119,9 +1120,8 @@ FullO3CPU<Impl>::drain(Event *drain_event) DPRINTF(O3CPU, "Switching out\n"); // If the CPU isn't doing anything, then return immediately. - if (_status == Idle || _status == SwitchedOut) { + if (_status == SwitchedOut) return 0; - } drainCount = 0; fetch.drain(); @@ -1142,6 +1142,8 @@ FullO3CPU<Impl>::drain(Event *drain_event) wakeCPU(); activityRec.activity(); + DPRINTF(Drain, "CPU not drained\n"); + return 1; } else { return 0; @@ -1160,7 +1162,7 @@ FullO3CPU<Impl>::resume() changeState(SimObject::Running); - if (_status == SwitchedOut || _status == Idle) + if (_status == SwitchedOut) return; assert(system->getMemoryMode() == Enums::timing); @@ -1183,6 +1185,7 @@ FullO3CPU<Impl>::signalDrained() BaseCPU::switchOut(); if (drainEvent) { + DPRINTF(Drain, "CPU done draining, processing drain event\n"); drainEvent->process(); drainEvent = NULL; } @@ -1237,6 +1240,10 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) assert(!tickEvent.scheduled() || tickEvent.squashed()); + FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); + if (oldO3CPU) + globalSeqNum = oldO3CPU->globalSeqNum; + // @todo: Figure out how to properly select the tid to put onto // the active threads list. ThreadID tid = 0; |