arch: cpu: Stop passing around misc registers by reference.

These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.

Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 431eb0f2f..90024bc84 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -390,12 +390,12 @@ class FullO3CPU : public BaseO3CPU
     RegVal readMiscReg(int misc_reg, ThreadID tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid);
+    void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid);
+    void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
 
     RegVal readIntReg(PhysRegIdPtr phys_reg);