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author | Anthony Gutierrez <atgutier@umich.edu> | 2013-11-15 13:21:15 -0500 |
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committer | Anthony Gutierrez <atgutier@umich.edu> | 2013-11-15 13:21:15 -0500 |
commit | 8a53da22c2f07aed924a45ab296f7468d842d7f6 (patch) | |
tree | 14f1df0a4b3aa217840384e3dee2ce53270e570d /src/cpu/o3/fetch.hh | |
parent | f028da7af7792bec226372ef23c1d103ad68ad30 (diff) | |
download | gem5-8a53da22c2f07aed924a45ab296f7468d842d7f6.tar.xz |
cpu: allow the fetch buffer to be smaller than a cache line
the current implementation of the fetch buffer in the o3 cpu
is only allowed to be the size of a cache line. some
architectures, e.g., ARM, have fetch buffers smaller than a cache
line, see slide 22 at:
http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf
this patch allows the fetch buffer to be set to values smaller
than a cache line.
Diffstat (limited to 'src/cpu/o3/fetch.hh')
-rw-r--r-- | src/cpu/o3/fetch.hh | 31 |
1 files changed, 18 insertions, 13 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 35f58ff74..6ef604af3 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -274,9 +274,9 @@ class DefaultFetch bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); /** - * Fetches the cache line that contains fetch_PC. Returns any + * Fetches the cache line that contains the fetch PC. Returns any * fault that happened. Puts the data into the class variable - * cacheData. + * fetchBuffer, which may not hold the entire fetched cache line. * @param vaddr The memory address that is being fetched from. * @param ret_fault The fault reference that will be set to the result of * the icache access. @@ -339,10 +339,10 @@ class DefaultFetch */ void fetch(bool &status_change); - /** Align a PC to the start of an I-cache block. */ - Addr icacheBlockAlignPC(Addr addr) + /** Align a PC to the start of a fetch buffer block. */ + Addr fetchBufferAlignPC(Addr addr) { - return (addr & ~(cacheBlkMask)); + return (addr & ~(fetchBufferMask)); } /** The decoder. */ @@ -463,17 +463,22 @@ class DefaultFetch /** Cache block size. */ unsigned int cacheBlkSize; - /** Mask to get a cache block's address. */ - Addr cacheBlkMask; + /** The size of the fetch buffer in bytes. The fetch buffer + * itself may be smaller than a cache line. + */ + unsigned fetchBufferSize; + + /** Mask to align a fetch address to a fetch buffer boundary. */ + Addr fetchBufferMask; - /** The cache line being fetched. */ - uint8_t *cacheData[Impl::MaxThreads]; + /** The fetch data that is being fetched and buffered. */ + uint8_t *fetchBuffer[Impl::MaxThreads]; - /** The PC of the cacheline that has been loaded. */ - Addr cacheDataPC[Impl::MaxThreads]; + /** The PC of the first instruction loaded into the fetch buffer. */ + Addr fetchBufferPC[Impl::MaxThreads]; - /** Whether or not the cache data is valid. */ - bool cacheDataValid[Impl::MaxThreads]; + /** Whether or not the fetch buffer data is valid. */ + bool fetchBufferValid[Impl::MaxThreads]; /** Size of instructions. */ int instSize; |