diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-06-04 16:07:54 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-06-04 16:07:54 -0400 |
commit | 984c2a4ff677803ff7687a178f1dceb1f0204c30 (patch) | |
tree | 10dc244225a4e29a65a94cc83305a2d18d150526 /src/cpu/o3/inst_queue.hh | |
parent | 3156f601db2728d329d9eff272bfa324ebdb2a0c (diff) | |
parent | 8671d927d862cdbdf851e74cd07d131679faa7ed (diff) | |
download | gem5-984c2a4ff677803ff7687a178f1dceb1f0204c30.tar.xz |
Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
src/cpu/checker/o3_cpu_builder.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/thread_state.hh:
Hand merge.
--HG--
rename : cpu/activity.cc => src/cpu/activity.cc
rename : cpu/activity.hh => src/cpu/activity.hh
rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/checker/cpu_builder.cc
rename : cpu/checker/exec_context.hh => src/cpu/checker/exec_context.hh
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_cpu_builder.cc
rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc
rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh
rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc
rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh
rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh
rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh
rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc
rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh
rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh
rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh
rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh
rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh
rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh
rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh
rename : cpu/o3/dep_graph.hh => src/cpu/o3/dep_graph.hh
rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/fu_pool.cc => src/cpu/o3/fu_pool.cc
rename : cpu/o3/fu_pool.hh => src/cpu/o3/fu_pool.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq.hh => src/cpu/o3/lsq.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh
rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh
rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc
rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/ozone_impl.hh => src/cpu/ozone/ozone_impl.hh
rename : cpu/ozone/simple_impl.hh => src/cpu/ozone/simple_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
extra : convert_revision : b7be30474dd03dd3970e737a9d0489aeb2ead84f
Diffstat (limited to 'src/cpu/o3/inst_queue.hh')
-rw-r--r-- | src/cpu/o3/inst_queue.hh | 34 |
1 files changed, 28 insertions, 6 deletions
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh index 245601ccf..60a713020 100644 --- a/src/cpu/o3/inst_queue.hh +++ b/src/cpu/o3/inst_queue.hh @@ -94,6 +94,9 @@ class InstructionQueue /** Pointer back to the instruction queue. */ InstructionQueue<Impl> *iqPtr; + /** Should the FU be added to the list to be freed upon + * completing this event. + */ bool freeFU; public: @@ -118,6 +121,7 @@ class InstructionQueue /** Registers statistics. */ void regStats(); + /** Resets all instruction queue state. */ void resetState(); /** Sets CPU pointer. */ @@ -135,10 +139,13 @@ class InstructionQueue /** Sets the global time buffer. */ void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); + /** Switches out the instruction queue. */ void switchOut(); + /** Takes over execution from another CPU's thread. */ void takeOverFrom(); + /** Returns if the IQ is switched out. */ bool isSwitchedOut() { return switchedOut; } /** Number of entries needed for given amount of threads. */ @@ -173,6 +180,9 @@ class InstructionQueue */ void insertBarrier(DynInstPtr &barr_inst); + /** Returns the oldest scheduled instruction, and removes it from + * the list of instructions waiting to execute. + */ DynInstPtr getInstToExecute(); /** @@ -276,13 +286,15 @@ class InstructionQueue /** List of all the instructions in the IQ (some of which may be issued). */ std::list<DynInstPtr> instList[Impl::MaxThreads]; + /** List of instructions that are ready to be executed. */ std::list<DynInstPtr> instsToExecute; /** - * Struct for comparing entries to be added to the priority queue. This - * gives reverse ordering to the instructions in terms of sequence - * numbers: the instructions with smaller sequence numbers (and hence - * are older) will be at the top of the priority queue. + * Struct for comparing entries to be added to the priority queue. + * This gives reverse ordering to the instructions in terms of + * sequence numbers: the instructions with smaller sequence + * numbers (and hence are older) will be at the top of the + * priority queue. */ struct pqCompare { bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const @@ -395,6 +407,7 @@ class InstructionQueue */ unsigned commitToIEWDelay; + /** Is the IQ switched out. */ bool switchedOut; /** The sequence number of the squashed instruction. */ @@ -462,19 +475,28 @@ class InstructionQueue */ Stats::Scalar<> iqSquashedNonSpecRemoved; + /** Distribution of number of instructions in the queue. */ Stats::VectorDistribution<> queueResDist; + /** Distribution of the number of instructions issued. */ Stats::Distribution<> numIssuedDist; + /** Distribution of the cycles it takes to issue an instruction. */ Stats::VectorDistribution<> issueDelayDist; + /** Number of times an instruction could not be issued because a + * FU was busy. + */ Stats::Vector<> statFuBusy; // Stats::Vector<> dist_unissued; + /** Stat for total number issued for each instruction type. */ Stats::Vector2d<> statIssuedInstType; + /** Number of instructions issued per cycle. */ Stats::Formula issueRate; // Stats::Formula issue_stores; // Stats::Formula issue_op_rate; - Stats::Vector<> fuBusy; //cumulative fu busy - + /** Number of times the FU was busy. */ + Stats::Vector<> fuBusy; + /** Number of times the FU was busy per instruction issued. */ Stats::Formula fuBusyRate; }; |