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author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-20 14:04:41 +0800 |
commit | 04547cc295885bfd85d8b340e147c9c3faad86ab (patch) | |
tree | b890f8f863b58b0d88eb74f1e03dfd3c39dc3814 /src/cpu/o3/lsq.hh | |
parent | 823d9d177fded16af07114d70b5c26caaec6aa00 (diff) | |
download | gem5-04547cc295885bfd85d8b340e147c9c3faad86ab.tar.xz |
invisispec-1.0 source
Diffstat (limited to 'src/cpu/o3/lsq.hh')
-rw-r--r-- | src/cpu/o3/lsq.hh | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 6bc9b3d73..5a028e0c2 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -136,6 +136,23 @@ class LSQ { /** Same as above, but only for one thread. */ void writebackStores(ThreadID tid); + + /** [mengjia] + * Attempts to validate loads until all cache ports are used or the + * interface becomes blocked. + */ + int exposeLoads(); + /** Same as above, but only for one thread. */ + int exposeLoads(ThreadID tid); + + /** [mengjia] + * attempt to update FenceDelay state for load insts + */ + void updateVisibleState(); + /** Same as above, but only for one thread. */ + void updateVisibleState(ThreadID tid); + + /** * Squash instructions from a thread until the specified sequence number. */ @@ -257,6 +274,10 @@ class LSQ { int numStoresToWB(ThreadID tid) { return thread[tid].numStoresToWB(); } + /** Returns the number of stores a specific thread has to write back. */ + int numLoadsToVLD(ThreadID tid) + { return thread[tid].numLoadsToVLD(); } + /** Returns if the LSQ will write back to memory this cycle. */ bool willWB(); /** Returns if the LSQ of a specific thread will write back to memory this |