diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-06-05 18:14:39 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-06-05 18:14:39 -0400 |
commit | 090496bf2d4c0f55f7f5869a374b4ec3826bccbc (patch) | |
tree | 4be899992389661b5cd60f2f067e39e719577430 /src/cpu/o3/lsq_unit_impl.hh | |
parent | 295c7a908cfeecc7276f559ff53282a177f4eb66 (diff) | |
download | gem5-090496bf2d4c0f55f7f5869a374b4ec3826bccbc.tar.xz |
Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses.
src/cpu/base_dyn_inst.cc:
Delete the allocated data in destructor.
src/cpu/base_dyn_inst.hh:
Only copy the addresses if the translation succeeded.
src/cpu/o3/alpha_cpu.hh:
Return actual translating port.
Don't panic on setNextNPC() as it's always called, regardless of the architecture, when the process initializes.
src/cpu/o3/alpha_cpu_impl.hh:
Pass in memobject to the thread state in SE mode.
src/cpu/o3/commit_impl.hh:
Initialize all variables.
src/cpu/o3/decode_impl.hh:
Handle early resolution of branches properly.
src/cpu/o3/fetch.hh:
Switch structure back to requests.
src/cpu/o3/fetch_impl.hh:
Initialize all variables, create/delete requests properly.
src/cpu/o3/lsq_unit.hh:
Include sender state along with the packet. Also include a more generic writeback event that's only used for stores forwarding data to loads.
src/cpu/o3/lsq_unit_impl.hh:
Redo writeback code to support the response path of the memory system.
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/mem_dep_unit_impl.hh:
Wrap variables in #ifdefs.
src/cpu/o3/store_set.cc:
Include to get panic() function.
src/cpu/o3/thread_state.hh:
Create with MemObject as well.
src/cpu/thread_state.hh:
Have a translating port in the thread state object.
src/python/m5/objects/AlphaFullCPU.py:
Mem parameter no longer needed.
--HG--
extra : convert_revision : a99381fb25cb183322882ce20935a6f3d1f2b64d
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 164 |
1 files changed, 91 insertions, 73 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 1ad561dc0..5398426e2 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -32,65 +32,57 @@ #include "mem/request.hh" template<class Impl> -void -LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) +LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, + LSQUnit *lsq_ptr) + : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) { -/* - DPRINTF(IEW, "Load writeback event [sn:%lli]\n", inst->seqNum); - DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum); - - //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); - - if (iewStage->isSwitchedOut()) { - inst = NULL; - return; - } else if (inst->isSquashed()) { - iewStage->wakeCPU(); - inst = NULL; - return; - } - - iewStage->wakeCPU(); - - if (!inst->isExecuted()) { - inst->setExecuted(); + this->setFlags(Event::AutoDelete); +} - // Complete access to copy data to proper place. - inst->completeAcc(); +template<class Impl> +void +LSQUnit<Impl>::WritebackEvent::process() +{ + if (!lsqPtr->isSwitchedOut()) { + lsqPtr->writeback(inst, pkt); } + delete pkt; +} - // Need to insert instruction into queue to commit - iewStage->instToCommit(inst); - - iewStage->activityThisCycle(); - - inst = NULL; -*/ +template<class Impl> +const char * +LSQUnit<Impl>::WritebackEvent::description() +{ + return "Store writeback event"; } template<class Impl> void -LSQUnit<Impl>::completeStoreDataAccess(DynInstPtr &inst) +LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) { -/* - DPRINTF(LSQ, "Cache miss complete for store idx:%i\n", storeIdx); - DPRINTF(Activity, "Activity: st writeback event idx:%i\n", storeIdx); + LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); + DynInstPtr inst = state->inst; + DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); +// DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum); - //lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum); - - if (lsqPtr->isSwitchedOut()) { - if (wbEvent) - delete wbEvent; + //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); + if (isSwitchedOut() || inst->isSquashed()) { + delete state; + delete pkt; return; - } + } else { + if (!state->noWB) { + writeback(inst, pkt); + } - lsqPtr->cpu->wakeCPU(); + if (inst->isStore()) { + completeStore(state->idx); + } + } - if (wb) - lsqPtr->completeDataAccess(storeIdx); - lsqPtr->completeStore(storeIdx); -*/ + delete state; + delete pkt; } template <class Impl> @@ -146,7 +138,8 @@ LSQUnit<Impl>::DcachePort::recvRetry() template <class Impl> LSQUnit<Impl>::LSQUnit() - : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false), + : loads(0), stores(0), storesToWB(0), stalled(false), + isStoreBlocked(false), isLoadBlocked(false), loadBlockedHandled(false) { } @@ -176,9 +169,7 @@ LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries, usedPorts = 0; cachePorts = params->cachePorts; - Port *mem_dport = params->mem->getPort(""); - dcachePort->setPeer(mem_dport); - mem_dport->setPeer(dcachePort); + mem = params->mem; memDepViolator = NULL; @@ -191,6 +182,10 @@ LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; dcachePort = new DcachePort(cpu, this); + + Port *mem_dport = mem->getPort(""); + dcachePort->setPeer(mem_dport); + mem_dport->setPeer(dcachePort); } template<class Impl> @@ -446,7 +441,6 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) int load_idx = store_inst->lqIdx; Fault store_fault = store_inst->initiateAcc(); -// Fault store_fault = store_inst->execute(); if (storeQueue[store_idx].size == 0) { DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", @@ -562,6 +556,12 @@ LSQUnit<Impl>::writebackStores() storeQueue[storeWBIdx].canWB && usedPorts < cachePorts) { + if (isStoreBlocked) { + DPRINTF(LSQUnit, "Unable to write back any more stores, cache" + " is blocked!\n"); + break; + } + // Store didn't write any data so no need to write it back to // memory. if (storeQueue[storeWBIdx].size == 0) { @@ -571,13 +571,7 @@ LSQUnit<Impl>::writebackStores() continue; } -/* - if (dcacheInterface && dcacheInterface->isBlocked()) { - DPRINTF(LSQUnit, "Unable to write back any more stores, cache" - " is blocked!\n"); - break; - } -*/ + ++usedPorts; if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { @@ -596,11 +590,18 @@ LSQUnit<Impl>::writebackStores() assert(!inst->memData); inst->memData = new uint8_t[64]; - memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, req->getSize()); + memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, + req->getSize()); PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); data_pkt->dataStatic(inst->memData); + LSQSenderState *state = new LSQSenderState; + state->isLoad = false; + state->idx = storeWBIdx; + state->inst = inst; + data_pkt->senderState = state; + DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " "to Addr:%#x, data:%#x [sn:%lli]\n", storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), @@ -609,11 +610,8 @@ LSQUnit<Impl>::writebackStores() if (!dcachePort->sendTiming(data_pkt)) { // Need to handle becoming blocked on a store. + isStoreBlocked = true; } else { - /* - StoreCompletionEvent *store_event = new - StoreCompletionEvent(storeWBIdx, NULL, this); - */ if (isStalled() && storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " @@ -623,18 +621,13 @@ LSQUnit<Impl>::writebackStores() stallingStoreIsn = 0; iewStage->replayMemInst(loadQueue[stallingLoadIdx]); } -/* - typename LdWritebackEvent *wb = NULL; - if (req->flags & LOCKED) { - // Stx_C should not generate a system port transaction - // if it misses in the cache, but that might be hard - // to accomplish without explicit cache support. - wb = new typename - LdWritebackEvent(storeQueue[storeWBIdx].inst, - iewStage); - store_event->wbEvent = wb; + + if (!(req->getFlags() & LOCKED)) { + assert(!storeQueue[storeWBIdx].inst->isStoreConditional()); + // Non-store conditionals do not need a writeback. + state->noWB = true; } -*/ + if (data_pkt->result != Packet::Success) { DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", storeWBIdx); @@ -761,6 +754,31 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) template <class Impl> void +LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) +{ + iewStage->wakeCPU(); + + // Squashed instructions do not need to complete their access. + if (inst->isSquashed()) { + assert(!inst->isStore()); + return; + } + + if (!inst->isExecuted()) { + inst->setExecuted(); + + // Complete access to copy data to proper place. + inst->completeAcc(pkt); + } + + // Need to insert instruction into queue to commit + iewStage->instToCommit(inst); + + iewStage->activityThisCycle(); +} + +template <class Impl> +void LSQUnit<Impl>::completeStore(int store_idx) { assert(storeQueue[store_idx].inst); |