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author | Kevin Lim <ktlim@umich.edu> | 2006-07-07 17:33:24 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-07-07 17:33:24 -0400 |
commit | 8ade33d324218737c815935120307153975eeadc (patch) | |
tree | 587a5dce799c0f5a2901dd1eaf452b2ae1ccfbc5 /src/cpu/o3/lsq_unit_impl.hh | |
parent | 744e0055b704f4c202e765f46e4fd4f56e1b847c (diff) | |
download | gem5-8ade33d324218737c815935120307153975eeadc.tar.xz |
Support Ron's changes for hooking up ports.
src/cpu/checker/cpu.hh:
Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
Add ports to the parameters.
--HG--
extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index bb3da7eec..8e951534f 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -182,10 +182,6 @@ LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) cpu = cpu_ptr; dcachePort = new DcachePort(cpu, this); - Port *mem_dport = mem->getPort(""); - dcachePort->setPeer(mem_dport); - mem_dport->setPeer(dcachePort); - #if USE_CHECKER if (cpu->checker) { cpu->checker->setDcachePort(dcachePort); |