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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:02 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:02 -0600 |
| commit | 0f9a3671b6d12f887501bc80ca50bb23c383686d (patch) | |
| tree | 5406b672b12e85c0654362272350cb50057be595 /src/cpu/o3/lsq_unit_impl.hh | |
| parent | 96375409ea7a5593ddd7f4f723db349921f35142 (diff) | |
| download | gem5-0f9a3671b6d12f887501bc80ca50bb23c383686d.tar.xz | |
ARM: Add support for moving predicated false dest operands from sources.
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 64d674666..7be5e4e5b 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -458,6 +458,8 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst) // realizes there is activity. // Mark it as executed unless it is an uncached load that // needs to hit the head of commit. + if (inst->readPredicate() == false) + inst->forwardOldRegs(); DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", inst->seqNum, (load_fault != NoFault ? "fault" : "predication")); @@ -530,6 +532,9 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) Fault store_fault = store_inst->initiateAcc(); + if (store_inst->readPredicate() == false) + store_inst->forwardOldRegs(); + if (storeQueue[store_idx].size == 0) { DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", store_inst->pcState(), store_inst->seqNum); |