diff options
| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:33 -0400 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:33 -0400 |
| commit | 976f27487b57e968a326752fcf74747427733df6 (patch) | |
| tree | 16c9e61f702f21d82948b1f5b555ef1b7c543b15 /src/cpu/o3/lsq_unit_impl.hh | |
| parent | fd722946dd723bda5bd4aea5eedbda108141a550 (diff) | |
| download | gem5-976f27487b57e968a326752fcf74747427733df6.tar.xz | |
cpu: Change writeback modeling for outstanding instructions
As highlighed on the mailing list gem5's writeback modeling can impact
performance. This patch removes the limitation on maximum outstanding issued
instructions, however the number that can writeback in a single cycle is still
respected in instToCommit().
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index e6bb560af..b805ed4be 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -109,9 +109,7 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) } assert(!cpu->switchedOut()); - if (inst->isSquashed()) { - iewStage->decrWb(inst->seqNum); - } else { + if (!inst->isSquashed()) { if (!state->noWB) { if (!TheISA::HasUnalignedMemAcc || !state->isSplit || !state->isLoad) { @@ -1130,7 +1128,6 @@ LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) // Squashed instructions do not need to complete their access. if (inst->isSquashed()) { - iewStage->decrWb(inst->seqNum); assert(!inst->isStore()); ++lsqIgnoredResponses; return; |