diff options
author | Gabe Black <gabeblack@google.com> | 2018-10-18 17:34:08 -0700 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2019-01-22 21:15:45 +0000 |
commit | 230b892fa3f484a46f4cd77f889f8793416b91e2 (patch) | |
tree | 53b32ed7120d019399e36d04655487745bbba9ee /src/cpu/o3 | |
parent | 774770a6410abb129e2a19de1ca50d7c0c311fef (diff) | |
download | gem5-230b892fa3f484a46f4cd77f889f8793416b91e2.tar.xz |
arch: cpu: Stop passing around misc registers by reference.
These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.
Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/cpu.cc | 6 | ||||
-rw-r--r-- | src/cpu/o3/cpu.hh | 4 | ||||
-rw-r--r-- | src/cpu/o3/dyn_inst.hh | 4 | ||||
-rw-r--r-- | src/cpu/o3/thread_context.hh | 4 | ||||
-rw-r--r-- | src/cpu/o3/thread_context_impl.hh | 4 |
5 files changed, 10 insertions, 12 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index c65e509f9..600c89aa5 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1260,16 +1260,14 @@ FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, - const RegVal &val, ThreadID tid) +FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) { this->isa[tid]->setMiscRegNoEffect(misc_reg, val); } template <class Impl> void -FullO3CPU<Impl>::setMiscReg(int misc_reg, - const RegVal &val, ThreadID tid) +FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) { miscRegfileWrites++; this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 431eb0f2f..90024bc84 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -390,12 +390,12 @@ class FullO3CPU : public BaseO3CPU RegVal readMiscReg(int misc_reg, ThreadID tid); /** Sets a miscellaneous register. */ - void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid); + void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid); + void setMiscReg(int misc_reg, RegVal val, ThreadID tid); RegVal readIntReg(PhysRegIdPtr phys_reg); diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 9054b2089..5bd0f8e47 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -146,7 +146,7 @@ class BaseO3DynInst : public BaseDynInst<Impl> * might have as defined by the architecture. */ void - setMiscReg(int misc_reg, const RegVal &val) + setMiscReg(int misc_reg, RegVal val) { /** Writes to misc. registers are recorded and deferred until the * commit stage, when updateMiscRegs() is called. First, check if @@ -182,7 +182,7 @@ class BaseO3DynInst : public BaseDynInst<Impl> * might have as defined by the architecture. */ void - setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val) + setMiscRegOperand(const StaticInst *si, int idx, RegVal val) { const RegId& reg = si->destRegIdx(idx); assert(reg.isMiscReg()); diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 510e96432..c74936469 100644 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -331,11 +331,11 @@ class O3ThreadContext : public ThreadContext { return cpu->readMiscReg(misc_reg, thread->threadId()); } /** Sets a misc. register. */ - virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val); + virtual void setMiscRegNoEffect(int misc_reg, RegVal val); /** Sets a misc. register, including any side-effects the * write might have as defined by the architecture. */ - virtual void setMiscReg(int misc_reg, const RegVal &val); + virtual void setMiscReg(int misc_reg, RegVal val); virtual RegId flattenRegId(const RegId& regId) const; diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 086d2cfeb..e1d771740 100644 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -307,7 +307,7 @@ O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const template <class Impl> void -O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val) +O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val) { cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); @@ -317,7 +317,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val) #endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__ template <class Impl> void -O3ThreadContext<Impl>::setMiscReg(int misc_reg, const RegVal &val) +O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val) { cpu->setMiscReg(misc_reg, val, thread->threadId()); |