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author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/cpu/reg_class.hh | |
parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/cpu/reg_class.hh')
-rw-r--r-- | src/cpu/reg_class.hh | 93 |
1 files changed, 53 insertions, 40 deletions
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh index 549ebab26..25c882c58 100644 --- a/src/cpu/reg_class.hh +++ b/src/cpu/reg_class.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2016 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved *. @@ -26,6 +38,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Steve Reinhardt + * Nathanael Premillieu */ #ifndef __CPU__REG_CLASS_HH__ @@ -34,6 +47,7 @@ #include <cassert> #include <cstddef> +#include "arch/generic/types.hh" #include "arch/registers.hh" #include "config/the_isa.hh" @@ -50,50 +64,49 @@ enum RegClass { /// unhandled cases in some switch statements. const int NumRegClasses = MiscRegClass + 1; -/** - * Map a 'unified' architectural register index to its register class. - * The unified architectural register index space is used to represent - * all architectural register identifiers in a single contiguous - * index space. See http://gem5.org/Register_Indexing. - * - * @param reg_idx Unified-space register index - * @param rel_reg_idx Optional output param pointer; if non-NULL, location - * will be written with the relative register index for reg_idx - * - * @return Register class of reg_idx - */ -inline -RegClass regIdxToClass(TheISA::RegIndex reg_idx, - TheISA::RegIndex *rel_reg_idx = NULL) -{ - assert(reg_idx < TheISA::Max_Reg_Index); - RegClass cl; - int offset; +/// Register ID: describe an architectural register with its class and index. +/// This structure is used instead of just the register index to disambiguate +/// between different classes of registers. +/// For example, a integer register with index 3 is represented by +/// Regid(IntRegClass, 3). +struct RegId { + RegClass regClass; + RegIndex regIdx; + RegId() {}; + RegId(RegClass reg_class, RegIndex reg_idx) + : regClass(reg_class), regIdx(reg_idx) + {} - if (reg_idx < TheISA::FP_Reg_Base) { - cl = IntRegClass; - offset = 0; - } else if (reg_idx < TheISA::CC_Reg_Base) { - cl = FloatRegClass; - offset = TheISA::FP_Reg_Base; - } else if (reg_idx < TheISA::Misc_Reg_Base) { - // if there are no CC regs, the ISA should set - // CC_Reg_Base == Misc_Reg_Base so the if above - // never succeeds - cl = CCRegClass; - offset = TheISA::CC_Reg_Base; - } else { - cl = MiscRegClass; - offset = TheISA::Misc_Reg_Base; + bool operator==(const RegId& that) const { + return regClass == that.regClass && regIdx == that.regIdx; } - if (rel_reg_idx) - *rel_reg_idx = reg_idx - offset; - return cl; -} + bool operator!=(const RegId& that) const { + return !(*this==that); + } -/// Map enum values to strings for debugging -extern const char *RegClassStrings[]; + /** + * Returns true if this register is a zero register (needs to have a + * constant zero value throughout the execution) + */ + bool isZeroReg() const + { + return (regIdx == TheISA::ZeroReg && + (regClass == IntRegClass || + (THE_ISA == ALPHA_ISA && regClass == FloatRegClass))); + } + /** + * Return true if this register can be renamed + */ + bool isRenameable() + { + return regClass != MiscRegClass; + } + static const RegId zeroReg; +}; + +/// Map enum values to strings for debugging +extern const char *RegClassStrings[]; #endif // __CPU__REG_CLASS_HH__ |