diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
commit | 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (patch) | |
tree | 0868fb00a7546d90971bc18acd4f7b0bbce558c0 /src/cpu/thread_context.hh | |
parent | 3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (diff) | |
download | gem5-32daf6fc3fd34af0023ae74c2a1f8dd597f87242.tar.xz |
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
Diffstat (limited to 'src/cpu/thread_context.hh')
-rw-r--r-- | src/cpu/thread_context.hh | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 3e37572d8..8963553d5 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -84,7 +84,6 @@ class ThreadContext typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::MiscRegFile MiscRegFile; typedef TheISA::MiscReg MiscReg; public: @@ -234,6 +233,9 @@ class ThreadContext virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; + virtual int flattenIntIndex(int reg) = 0; + virtual int flattenFloatIndex(int reg) = 0; + virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid) { @@ -434,6 +436,12 @@ class ProxyThreadContext : public ThreadContext void setMiscReg(int misc_reg, const MiscReg &val) { return actualTC->setMiscReg(misc_reg, val); } + int flattenIntIndex(int reg) + { return actualTC->flattenIntIndex(reg); } + + int flattenFloatIndex(int reg) + { return actualTC->flattenFloatIndex(reg); } + unsigned readStCondFailures() { return actualTC->readStCondFailures(); } |