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authorGabe Black <gblack@eecs.umich.edu>2006-10-23 02:39:02 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-23 02:39:02 -0400
commite9908e3c854e534a391448907773ca03c60b13c8 (patch)
tree7d998a3bda07fa6ac4ecb137aad810ead0440835 /src/cpu
parenta8973c605416e82f18470bedb0cc764a016d2bd8 (diff)
downloadgem5-e9908e3c854e534a391448907773ca03c60b13c8.tar.xz
Don't let interupts interupt microcode at undesired points.
--HG-- extra : convert_revision : a8ddc6b213b1a1b0d9c5cd194b88ac0c6bfb2a21
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/simple/atomic.cc3
-rw-r--r--src/cpu/simple/timing.cc3
2 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 38a8ba097..25c478ae9 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -448,7 +448,8 @@ AtomicSimpleCPU::tick()
for (int i = 0; i < width; ++i) {
numCycles++;
- checkForInterrupts();
+ if (!curStaticInst || !curStaticInst->isDelayedCommit())
+ checkForInterrupts();
Fault fault = setupFetchRequest(ifetch_req);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 97df0e5d5..fe6775ea4 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -427,7 +427,8 @@ TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
void
TimingSimpleCPU::fetch()
{
- checkForInterrupts();
+ if (!curStaticInst || !curStaticInst->isDelayedCommit())
+ checkForInterrupts();
Request *ifetch_req = new Request();
ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);