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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-11 12:57:36 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 08:28:51 +0000 |
commit | ef984784289f8bd4ddedcc4a6ead2c45704cc35b (patch) | |
tree | 5aa675bf8edb27f8895deb8f05e1de8a66233107 /src/dev/arm/gic_v2.hh | |
parent | 058e2cec7c56bf0549efff1df5974799c41cd1be (diff) | |
download | gem5-ef984784289f8bd4ddedcc4a6ead2c45704cc35b.tar.xz |
dev-arm: Fix GICv2 cpu interrupt enable flag
Read/WriteCpu methods in the GICv2 are accessing the GICC_CTRL register
as if writing any non-zero value to the register will enable IRQ
signaling to the CPU. Instead, only the 2 least significant bits
control group0/group1 enablement. This patch is renaming GICC_CTRL
underlying data buffer from cpuEnabled to cpuControl and it is making it
an array of uint32_t instead of bool. cpuEnabled now becomes a method
and checks if GICC_CTRL.EnableGrp0 or GICC_CTRL.EnableGrp0 are set.
Change-Id: I40f0b3c52c40abd482a856f032bf3686f96ef641
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12945
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/arm/gic_v2.hh')
-rw-r--r-- | src/dev/arm/gic_v2.hh | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh index 352b108d0..2057e7d5b 100644 --- a/src/dev/arm/gic_v2.hh +++ b/src/dev/arm/gic_v2.hh @@ -142,6 +142,12 @@ class GicV2 : public BaseGic, public BaseGicRegisters Bitfield<12,10> cpu_id; EndBitUnion(IAR) + BitUnion32(CTLR) + Bitfield<3> fiqEn; + Bitfield<1> enableGrp1; + Bitfield<0> enableGrp0; + EndBitUnion(CTLR) + protected: /* Params */ /** Address range for the distributor interface */ const AddrRange distRange; @@ -310,7 +316,15 @@ class GicV2 : public BaseGic, public BaseGicRegisters } /** CPU enabled */ - bool cpuEnabled[CPU_MAX]; + bool cpuEnabled(ContextID ctx) const { + return cpuControl[ctx].enableGrp0 || + cpuControl[ctx].enableGrp1; + } + + /** GICC_CTLR: + * CPU interface control register + */ + CTLR cpuControl[CPU_MAX]; /** CPU priority */ uint8_t cpuPriority[CPU_MAX]; |