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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-08-15 14:24:49 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-08-15 14:24:49 -0400 |
commit | dc375e42bc739e8869a75993a93ed8afc3f294cc (patch) | |
tree | 1cc2077048477e2417b564c3e424ef3d71f3b9a3 /src/mem/cache/base_cache.cc | |
parent | f7216daee06189ec3f432dcce6de27b5b4380880 (diff) | |
download | gem5-dc375e42bc739e8869a75993a93ed8afc3f294cc.tar.xz |
Some changes to support blocking in the caches
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache_impl.hh:
Outstanding blocking updates for cache
--HG--
extra : convert_revision : 3a7b4aa4921de8239f604f1852f262a2305862c0
Diffstat (limited to 'src/mem/cache/base_cache.cc')
-rw-r--r-- | src/mem/cache/base_cache.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 451da28e8..9b1034577 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -71,6 +71,11 @@ BaseCache::CachePort::deviceBlockSize() bool BaseCache::CachePort::recvTiming(Packet *pkt) { + if (blocked) + { + mustSendRetry = true; + return false; + } return cache->doTimingAccess(pkt, this, isCpuSide); } @@ -95,6 +100,11 @@ BaseCache::CachePort::setBlocked() void BaseCache::CachePort::clearBlocked() { + if (mustSendRetry) + { + mustSendRetry = false; + sendRetry(); + } blocked = false; } |