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author | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-16 05:49:43 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-16 05:49:43 -0400 |
commit | df973abef3a70074971375cfe52c46f53528c00e (patch) | |
tree | 7c10603edb5c66631288cb0f9fa334df4cf3d8a9 /src/mem/cache/prefetch/Prefetcher.py | |
parent | 37908d62a4b45962a6e6f5993027b6b9bafa296d (diff) | |
download | gem5-df973abef3a70074971375cfe52c46f53528c00e.tar.xz |
mem: Dynamically determine page bytes in memory components
This patch takes a step towards an ISA-agnostic memory
system by enabling the components to establish the page size after
instantiation. The swap operation in the memory is now also allowing
any granularity to avoid depending on the IntReg of the ISA.
Diffstat (limited to 'src/mem/cache/prefetch/Prefetcher.py')
-rw-r--r-- | src/mem/cache/prefetch/Prefetcher.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index 6bb4e52d3..fed59661d 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -67,7 +67,7 @@ class BasePrefetcher(ClockedObject): "Let lower cache prefetcher train on prefetch requests") inst_tagged = Param.Bool(True, "Perform a tagged prefetch for instruction fetches always") - sys = Param.System(Parent.any, "System this device belongs to") + sys = Param.System(Parent.any, "System this prefetcher belongs to") class StridePrefetcher(BasePrefetcher): type = 'StridePrefetcher' |