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author | Andreas Hansson <andreas.hansson@arm.com> | 2015-12-31 09:32:58 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-12-31 09:32:58 -0500 |
commit | 0fcb376e5fc6bc0a7b16dc4595d4a7e3f910cbc8 (patch) | |
tree | 4be665e3596d9d4e193e6354c5577ee0077732da /src/mem/dramsim2.cc | |
parent | a3177645773b8eb4b835050c395554d3e2b4664a (diff) | |
download | gem5-0fcb376e5fc6bc0a7b16dc4595d4a7e3f910cbc8.tar.xz |
mem: Make cache terminology easier to understand
This patch changes the name of a bunch of packet flags and MSHR member
functions and variables to make the coherency protocol easier to
understand. In addition the patch adds and updates lots of
descriptions, explicitly spelling out assumptions.
The following name changes are made:
* the packet memInhibit flag is renamed to cacheResponding
* the packet sharedAsserted flag is renamed to hasSharers
* the packet NeedsExclusive attribute is renamed to NeedsWritable
* the packet isSupplyExclusive is renamed responderHadWritable
* the MSHR pendingDirty is renamed to pendingModified
The cache states, Modified, Owned, Exclusive, Shared are also called
out in the cache and MSHR code to make it easier to understand.
Diffstat (limited to 'src/mem/dramsim2.cc')
-rw-r--r-- | src/mem/dramsim2.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc index 58227e06a..fb1ee945b 100644 --- a/src/mem/dramsim2.cc +++ b/src/mem/dramsim2.cc @@ -155,7 +155,7 @@ DRAMSim2::recvAtomic(PacketPtr pkt) access(pkt); // 50 ns is just an arbitrary value at this point - return pkt->memInhibitAsserted() ? 0 : 50000; + return pkt->cacheResponding() ? 0 : 50000; } void @@ -175,8 +175,8 @@ DRAMSim2::recvFunctional(PacketPtr pkt) bool DRAMSim2::recvTimingReq(PacketPtr pkt) { - // sink inhibited packets without further action - if (pkt->memInhibitAsserted()) { + // if a cache is responding, sink the packet without further action + if (pkt->cacheResponding()) { pendingDelete.reset(pkt); return true; } |