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author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-01-04 00:03:31 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-01-04 00:03:31 -0600 |
commit | 5b1804e3bdb88aea7a198ff25617bb671cd34769 (patch) | |
tree | 38c8644bb17caaa708e6c678f0f495d7db5f74dc /src/mem/protocol/MESI_CMP_directory-L1cache.sm | |
parent | 9853ef6651e76883615595bf76f983ed43234f96 (diff) | |
download | gem5-5b1804e3bdb88aea7a198ff25617bb671cd34769.tar.xz |
ruby: add support for clusters
A cluster over here means a set of controllers that can be accessed only by a
certain set of cores. For example, consider a two level hierarchy. Assume
there are 4 L1 controllers (private) and 2 L2 controllers. We can have two
different hierarchies here:
a. the address space is partitioned between the two L2 controllers. Each L1
controller accesses both the L2 controllers. In this case, each L1 controller
is a cluster initself.
b. both the L2 controllers can cache any address. An L1 controller has access
to only one of the L2 controllers. In this case, each L2 controller
along with the L1 controllers that access it, form a cluster.
This patch allows for each controller to have a cluster ID, which is 0 by
default. By setting the cluster ID properly, one can instantiate hierarchies
with clusters. Note that the coherence protocol might have to be changed as
well.
Diffstat (limited to 'src/mem/protocol/MESI_CMP_directory-L1cache.sm')
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L1cache.sm | 32 |
1 files changed, 15 insertions, 17 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index 347e548bb..bd56b5660 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -500,7 +500,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; @@ -518,7 +518,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; @@ -535,7 +535,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Type := CoherenceRequestType:GET_INSTR; out_msg.Requestor := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; @@ -555,7 +555,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Requestor := machineID; out_msg.Destination.add( mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Control; out_msg.Prefetch := in_msg.Prefetch; out_msg.AccessMode := in_msg.AccessMode; @@ -574,7 +574,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Requestor := machineID; DPRINTF(RubySlicc, "%s\n", machineID); out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; @@ -593,10 +593,8 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Requestor := machineID; DPRINTF(RubySlicc, "%s\n", machineID); - out_msg.Destination.add(mapAddressToRange(address, - MachineType:L2Cache, - l2_select_low_bit, - l2_select_num_bits)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); @@ -614,7 +612,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Type := CoherenceRequestType:UPGRADE; out_msg.Requestor := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; @@ -648,7 +646,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Dirty := cache_entry.Dirty; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Response_Data; } } @@ -677,7 +675,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Dirty := tbe.Dirty; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Response_Data; } } @@ -703,7 +701,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Dirty := cache_entry.Dirty; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Writeback_Data; } } @@ -717,7 +715,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Dirty := tbe.Dirty; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Writeback_Data; } } @@ -751,7 +749,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Dirty := cache_entry.Dirty; out_msg.Requestor:= machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); if (cache_entry.Dirty) { out_msg.MessageSize := MessageSizeType:Writeback_Data; } else { @@ -766,7 +764,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Response_Control; DPRINTF(RubySlicc, "%s\n", address); } @@ -778,7 +776,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Response_Control; DPRINTF(RubySlicc, "%s\n", address); |