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author | Nathan Binkert <nate@binkert.org> | 2009-05-11 10:38:43 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2009-05-11 10:38:43 -0700 |
commit | 2f30950143cc70bc42a3c8a4111d7cf8198ec881 (patch) | |
tree | 708f6c22edb3c6feb31dd82866c26623a5329580 /src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm | |
parent | c70241810d4e4f523f173c1646b008dc40faad8e (diff) | |
download | gem5-2f30950143cc70bc42a3c8a4111d7cf8198ec881.tar.xz |
ruby: Import ruby and slicc from GEMS
We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
Diffstat (limited to 'src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm')
-rw-r--r-- | src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm b/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm new file mode 100644 index 000000000..80ab0f246 --- /dev/null +++ b/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm @@ -0,0 +1,115 @@ + +/* + * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + * + */ + +// CoherenceRequestType +enumeration(CoherenceRequestType, desc="...") { + GETX, desc="Get eXclusive"; + UPGRADE, desc="UPGRADE to exclusive"; + GETS, desc="Get Shared"; + GET_INSTR, desc="Get Instruction"; + PUTX, desc="Put eXclusive"; + PUTS, desc="Put Shared"; + INV, desc="INValidate"; + INV_S, desc="INValidate the shared version"; + L1_DG, desc="L1 cache DownGrade"; + WB_ACK, desc="Write Back ACKnowledgment"; + EXE_ACK, desc="EXclusivE ACKnowledgment"; +} + +// CoherenceResponseType +enumeration(CoherenceResponseType, desc="...") { + ACK, desc="ACKnowledgment"; + INV_ACK, desc="INValidation ACKnowledgment"; + DG_ACK, desc="DownGrade ACKnowledgment"; + NACK, desc="Negative ACKnowledgment"; + DATA, desc="Data"; + DATA_S, desc="Data to L1 cache, then imediately go to shared state"; + DATA_I, desc="Data to L1 cache, then imediately go to inv state"; + FINALACK, desc=""; +} + +// RequestMsg +structure(RequestMsg, desc="...", interface="NetworkMessage") { + Address Address, desc="Physical address for this request"; + CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)"; + AccessModeType AccessMode, desc="user/supervisor access type"; + MachineID RequestorMachId, desc="What component request"; + NetDest Destination, desc="What components receive the request, includes MachineType and num"; + DataBlock DataBlk, desc="Data for the cache line (if PUTX)"; + int NumPendingExtAcks, desc="Number of acks to wait for"; // Needed for forwarded responses only + MessageSizeType MessageSize, desc="size category of the message"; + string L1CacheStateStr, desc="describes L1 cache block state"; + string L2CacheStateStr, desc="describes L2 cache block state"; + PrefetchBit Prefetch, desc="Is this a prefetch request"; +} + +// ResponseMsg +structure(ResponseMsg, desc="...", interface="NetworkMessage") { + Address Address, desc="Physical address for this request"; + CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)"; + MachineID SenderMachId, desc="What component sent the data"; + NetDest Destination, desc="Node to whom the data is sent"; + DataBlock DataBlk, desc="data for the cache line"; + int NumPendingExtAcks, desc="Number of acks to wait for"; + MessageSizeType MessageSize, desc="size category of the message"; +} + +GenericRequestType convertToGenericType(CoherenceRequestType type) { + if(type == CoherenceRequestType:PUTX) { + return GenericRequestType:PUTX; + } else if(type == CoherenceRequestType:GETS) { + return GenericRequestType:GETS; + } else if(type == CoherenceRequestType:GET_INSTR) { + return GenericRequestType:GET_INSTR; + } else if(type == CoherenceRequestType:GETX) { + return GenericRequestType:GETX; + } else if(type == CoherenceRequestType:UPGRADE) { + return GenericRequestType:UPGRADE; + } else if(type == CoherenceRequestType:PUTS) { + return GenericRequestType:PUTS; + } else if(type == CoherenceRequestType:INV) { + return GenericRequestType:INV; + } else if(type == CoherenceRequestType:INV_S) { + return GenericRequestType:INV_S; + } else if(type == CoherenceRequestType:L1_DG) { + return GenericRequestType:DOWNGRADE; + } else if(type == CoherenceRequestType:WB_ACK) { + return GenericRequestType:WB_ACK; + } else if(type == CoherenceRequestType:EXE_ACK) { + return GenericRequestType:EXE_ACK; + } else { + DEBUG_EXPR(type); + error("invalid CoherenceRequestType"); + } +} |