diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2016-01-11 05:52:20 -0500 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-01-11 05:52:20 -0500 |
commit | 12eb0343784f52994110df7e7fce4a0b639a6ec3 (patch) | |
tree | 12ff1c51b8051bb7e7d889eed499bee0dcd4cd1e /src/mem/ruby | |
parent | 7661f1c2bf2b45603264076fabce2eb42373cd18 (diff) | |
download | gem5-12eb0343784f52994110df7e7fce4a0b639a6ec3.tar.xz |
scons: Enable -Wextra by default
Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.
Diffstat (limited to 'src/mem/ruby')
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 4 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/Message.hh | 6 | ||||
-rw-r--r-- | src/mem/ruby/structures/RubyMemoryControl.cc | 10 | ||||
-rw-r--r-- | src/mem/ruby/structures/RubyMemoryControl.hh | 10 | ||||
-rw-r--r-- | src/mem/ruby/system/RubySystem.hh | 2 |
5 files changed, 16 insertions, 16 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 34160c149..383507eed 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -65,8 +65,8 @@ class AbstractController : public MemObject, public Consumer void init(); const Params *params() const { return (const Params *)_params; } - const NodeID getVersion() const { return m_machineID.getNum(); } - const MachineType getType() const { return m_machineID.getType(); } + NodeID getVersion() const { return m_machineID.getNum(); } + MachineType getType() const { return m_machineID.getType(); } void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh index 587103101..c62b4e123 100644 --- a/src/mem/ruby/slicc_interface/Message.hh +++ b/src/mem/ruby/slicc_interface/Message.hh @@ -83,12 +83,12 @@ class Message Tick delta = curTime - m_LastEnqueueTime; m_DelayedTicks += delta; } - const Tick getDelayedTicks() const {return m_DelayedTicks;} + Tick getDelayedTicks() const {return m_DelayedTicks;} void setLastEnqueueTime(const Tick& time) { m_LastEnqueueTime = time; } - const Tick getLastEnqueueTime() const {return m_LastEnqueueTime;} + Tick getLastEnqueueTime() const {return m_LastEnqueueTime;} - const Tick& getTime() const { return m_time; } + Tick getTime() const { return m_time; } void setMsgCounter(uint64_t c) { m_msg_counter = c; } uint64_t getMsgCounter() const { return m_msg_counter; } diff --git a/src/mem/ruby/structures/RubyMemoryControl.cc b/src/mem/ruby/structures/RubyMemoryControl.cc index 5feb9348b..77f1c239f 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.cc +++ b/src/mem/ruby/structures/RubyMemoryControl.cc @@ -342,7 +342,7 @@ RubyMemoryControl::enqueueToDirectory(MemoryNode *req, Cycles latency) // getBank returns an integer that is unique for each // bank across this memory controller. -const int +int RubyMemoryControl::getBank(const Addr addr) const { int dimm = (addr >> m_dimm_bit_0) & (m_dimms_per_channel - 1); @@ -353,7 +353,7 @@ RubyMemoryControl::getBank(const Addr addr) const + bank; } -const int +int RubyMemoryControl::getRank(const Addr addr) const { int bank = getBank(addr); @@ -364,7 +364,7 @@ RubyMemoryControl::getRank(const Addr addr) const // getRank returns an integer that is unique for each rank // and independent of individual bank. -const int +int RubyMemoryControl::getRank(int bank) const { int rank = (bank / m_banks_per_rank); @@ -373,7 +373,7 @@ RubyMemoryControl::getRank(int bank) const } // Not used! -const int +int RubyMemoryControl::getChannel(const Addr addr) const { assert(false); @@ -381,7 +381,7 @@ RubyMemoryControl::getChannel(const Addr addr) const } // Not used! -const int +int RubyMemoryControl::getRow(const Addr addr) const { assert(false); diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh index cd777f5e7..601c4d1a2 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.hh +++ b/src/mem/ruby/structures/RubyMemoryControl.hh @@ -75,12 +75,12 @@ class RubyMemoryControl : public AbstractMemory, public Consumer void print(std::ostream& out) const override; void regStats() override; - const int getBank(const Addr addr) const; - const int getRank(const Addr addr) const; + int getBank(const Addr addr) const; + int getRank(const Addr addr) const; // not used in Ruby memory controller - const int getChannel(const Addr addr) const; - const int getRow(const Addr addr) const; + int getChannel(const Addr addr) const; + int getRow(const Addr addr) const; //added by SS int getBanksPerRank() { return m_banks_per_rank; }; @@ -92,7 +92,7 @@ class RubyMemoryControl : public AbstractMemory, public Consumer private: void enqueueToDirectory(MemoryNode *req, Cycles latency); - const int getRank(int bank) const; + int getRank(int bank) const; bool queueReady(int bank); void issueRequest(int bank); bool issueRefresh(int bank); diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh index e396dce64..62330e19d 100644 --- a/src/mem/ruby/system/RubySystem.hh +++ b/src/mem/ruby/system/RubySystem.hh @@ -79,7 +79,7 @@ class RubySystem : public ClockedObject SimpleMemory *getPhysMem() { return m_phys_mem; } Cycles getStartCycle() { return m_start_cycle; } - const bool getAccessBackingStore() { return m_access_backing_store; } + bool getAccessBackingStore() { return m_access_backing_store; } // Public Methods Profiler* |