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author | David Guillen-Fandos <david.guillen@arm.com> | 2015-07-30 03:41:42 -0400 |
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committer | David Guillen-Fandos <david.guillen@arm.com> | 2015-07-30 03:41:42 -0400 |
commit | 0c89c15b23d4db50eb08f8ebf2a40b569f41dd29 (patch) | |
tree | 9f5e2bcf48d88e940b9fea6b2fa9f37d05ea2741 /src/mem/slicc/main.py | |
parent | 5a18e181ffb8fbef5f4aca8fb9a63ee6a7c9e0d6 (diff) | |
download | gem5-0c89c15b23d4db50eb08f8ebf2a40b569f41dd29.tar.xz |
mem: Make caches way aware
This patch makes cache sets aware of the way number. This enables
some nice features such as the ablity to restrict way allocation. The
implemented mechanism allows to set a maximum way number to be
allocated 'k' which must fulfill 0 < k <= N (where N is the number of
ways). In the future more sophisticated mechasims can be implemented.
Diffstat (limited to 'src/mem/slicc/main.py')
0 files changed, 0 insertions, 0 deletions