summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2007-09-06 16:22:08 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-09-06 16:22:08 -0700
commit5052e2cb10b78da55ddef2b1deb67ab2e2aa3255 (patch)
treed04b0ccb1c28491a1a0884023c2dc2a152919a3e /src
parent832ef7412b7ab35cb50613fb1b53bd32c48d5a1f (diff)
downloadgem5-5052e2cb10b78da55ddef2b1deb67ab2e2aa3255.tar.xz
X86: Make signed versions of partial register values available to microops.
--HG-- extra : convert_revision : c820d1250f505911a341ced42d4f73796ea77f87
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/insts/static_inst.hh21
-rw-r--r--src/arch/x86/intregs.hh5
-rw-r--r--src/arch/x86/isa/microops/regop.isa13
3 files changed, 36 insertions, 3 deletions
diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh
index 22139fc77..e5c333e75 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -140,6 +140,27 @@ namespace X86ISA
panic("Tried to pick with unrecognized size %d.\n", size);
}
}
+
+ inline int64_t signedPick(uint64_t from, int idx, int size) const
+ {
+ X86IntReg reg = from;
+ DPRINTF(X86, "Picking with size %d\n", size);
+ if(_srcRegIdx[idx] & (1 << 6))
+ return reg.SH;
+ switch(size)
+ {
+ case 1:
+ return reg.SL;
+ case 2:
+ return reg.SX;
+ case 4:
+ return reg.SE;
+ case 8:
+ return reg.SR;
+ default:
+ panic("Tried to pick with unrecognized size %d.\n", size);
+ }
+ }
};
}
diff --git a/src/arch/x86/intregs.hh b/src/arch/x86/intregs.hh
index bfec7d041..dbbb9f97e 100644
--- a/src/arch/x86/intregs.hh
+++ b/src/arch/x86/intregs.hh
@@ -64,10 +64,15 @@ namespace X86ISA
{
BitUnion64(X86IntReg)
Bitfield<63,0> R;
+ SignedBitfield<63,0> SR;
Bitfield<31,0> E;
+ SignedBitfield<31,0> SE;
Bitfield<15,0> X;
+ SignedBitfield<15,0> SX;
Bitfield<15,8> H;
+ SignedBitfield<15,8> SH;
Bitfield<7, 0> L;
+ SignedBitfield<7, 0> SL;
EndBitUnion(X86IntReg)
enum IntRegIndex
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 60089085f..6d68f4fe9 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -283,10 +283,17 @@ let {{
# compute it.
matcher = re.compile("(?<!\w)psrc1(?!\w)")
if matcher.search(allCode):
- code = "IntReg psrc1 = pick(SrcReg1, 0, dataSize);" + code
+ code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
matcher = re.compile("(?<!\w)psrc2(?!\w)")
if matcher.search(allCode):
- code = "IntReg psrc2 = pick(SrcReg2, 1, dataSize);" + code
+ code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
+ # Also make available versions which do sign extension
+ matcher = re.compile("(?<!\w)spsrc1(?!\w)")
+ if matcher.search(allCode):
+ code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
+ matcher = re.compile("(?<!\w)spsrc2(?!\w)")
+ if matcher.search(allCode):
+ code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
base = "X86ISA::RegOp"
@@ -671,7 +678,7 @@ let {{
#FIXME This needs to always use 32 bits unless REX.W is present
class cvtf_i2d(ConvOp):
- code = 'FpDestReg = psrc1;'
+ code = 'FpDestReg = spsrc1;'
class cvtf_i2d_hi(ConvOp):
code = 'FpDestReg = bits(SrcReg1, 63, 32);'