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authorAli Saidi <Ali.Saidi@ARM.com>2012-01-09 18:08:20 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2012-01-09 18:08:20 -0600
commit80a6907927461241883a47b552272702978216f8 (patch)
tree4cfb467aa115465241653336f7ab3ed345ad8251 /src
parent3f9e352de4e1ac34e1f0b83c3f66af2175b524f4 (diff)
downloadgem5-80a6907927461241883a47b552272702978216f8.tar.xz
ARM: Add support for initparam m5 op
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/isa/insts/m5ops.isa8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index 3b837cba9..f20908d4f 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -191,16 +191,18 @@ let {{
initparamCode = '''
#if FULL_SYSTEM
- Rt = PseudoInst::initParam(xc->tcBase());
+ uint64_t ip_val = PseudoInst::initParam(xc->tcBase());
+ R0 = bits(ip_val, 31, 0);
+ R1 = bits(ip_val, 63, 32);
#else
PseudoInst::panicFsOnlyPseudoInst("initparam");
- Rt = 0;
#endif
'''
initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
{ "code": initparamCode,
- "predicate_test": predicateTest })
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative"])
header_output += BasicDeclare.subst(initparamIop)
decoder_output += BasicConstructor.subst(initparamIop)
exec_output += PredOpExecute.subst(initparamIop)