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author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-03-20 09:14:14 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-03-20 09:14:14 -0500 |
commit | b5cc4c760478240bf8c5f7de977bf2b56fd8dfd4 (patch) | |
tree | f4d9bf0eee60c59b294f8e25504e67e58bfdd1f6 /tests/configs/pc-simple-timing-ruby.py | |
parent | f2059f8399b22ecc544413a0e9d5a13a6f965411 (diff) | |
download | gem5-b5cc4c760478240bf8c5f7de977bf2b56fd8dfd4.tar.xz |
config: ruby: rename _cpu_ruby_ports to _cpu_ports
Diffstat (limited to 'tests/configs/pc-simple-timing-ruby.py')
-rw-r--r-- | tests/configs/pc-simple-timing-ruby.py | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 3d1b78324..2ac571c83 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -78,16 +78,16 @@ for (i, cpu) in enumerate(system.cpu): # create the interrupt controller cpu.createInterruptController() # Tie the cpu ports to the correct ruby system ports - cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave - cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave - cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave - cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave - cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master - cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave - cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master + cpu.icache_port = system.ruby._cpu_ports[i].slave + cpu.dcache_port = system.ruby._cpu_ports[i].slave + cpu.itb.walker.port = system.ruby._cpu_ports[i].slave + cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave + cpu.interrupts.pio = system.ruby._cpu_ports[i].master + cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave + cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master # Set access_phys_mem to True for ruby port - system.ruby._cpu_ruby_ports[i].access_phys_mem = True + system.ruby._cpu_ports[i].access_phys_mem = True system.physmem = [DDR3_1600_x64(range = r) for r in system.mem_ranges] |