alpha:o3:simple: update simout/err files

A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning

Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.

1 files changed, 39 insertions, 39 deletions

diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index fdb2e2919..b2d2b0068 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,66 +1,66 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                6401056                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 195828                       # Number of bytes of host memory used
-host_seconds                                    94.02                       # Real time elapsed on the host
-host_tick_rate                             3200547989                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.300931                       # Number of seconds simulated
 sim_ticks                                300930958000                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                153970296                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    153965363                       # DTB hits
-system.cpu.dtb.data_misses                       4933                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3663682                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1831855621                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 184012                       # Number of bytes of host memory used
+host_seconds                                   164.28                       # Real time elapsed on the host
+sim_insts                                   601856964                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                114516673                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                    114514042                       # DTB read hits
 system.cpu.dtb.read_misses                       2631                       # DTB read misses
-system.cpu.dtb.write_accesses                39453623                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                114516673                       # DTB read accesses
 system.cpu.dtb.write_hits                    39451321                       # DTB write hits
 system.cpu.dtb.write_misses                      2302                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses               601861917                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                39453623                       # DTB write accesses
+system.cpu.dtb.data_hits                    153965363                       # DTB hits
+system.cpu.dtb.data_misses                       4933                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                153970296                       # DTB accesses
 system.cpu.itb.fetch_hits                   601861897                       # ITB hits
 system.cpu.itb.fetch_misses                        20                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               601861917                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 system.cpu.numCycles                        601861917                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  601861917                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     58554292                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
-system.cpu.num_fp_insts                          1520                       # number of float instructions
-system.cpu.num_fp_register_reads                  169                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  42                       # number of times the floating registers were written
-system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                        601856964                       # Number of instructions executed
 system.cpu.num_int_alu_accesses             563959696                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
+system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     58554292                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    563959696                       # number of integer instructions
+system.cpu.num_fp_insts                          1520                       # number of float instructions
 system.cpu.num_int_register_reads           801088993                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          463854847                       # number of times the integer registers were written
-system.cpu.num_load_insts                   114516673                       # Number of load instructions
+system.cpu.num_fp_register_reads                  169                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  42                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     153970296                       # number of memory refs
+system.cpu.num_load_insts                   114516673                       # Number of load instructions
 system.cpu.num_store_insts                   39453623                       # Number of store instructions
-system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  601861917                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------