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authorSteve Reinhardt <stever@gmail.com>2009-02-16 12:09:45 -0500
committerSteve Reinhardt <stever@gmail.com>2009-02-16 12:09:45 -0500
commit89ea32325094665c16688212b5a2cd7b7bbf5f03 (patch)
tree2259a04ed0e6c700096d8f662726c51a2c6da525 /tests/long/00.gzip/ref/sparc
parent89a7fb03934b3e38c7d8b2c4818794b3ec874fdf (diff)
downloadgem5-89ea32325094665c16688212b5a2cd7b7bbf5f03.tar.xz
Update stats for new prefetching fixes.
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
Diffstat (limited to 'tests/long/00.gzip/ref/sparc')
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini12
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/o3-timing/simerr3
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/o3-timing/simout9
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt35
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini3
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr3
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-atomic/simout9
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt8
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini12
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-timing/simerr3
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-timing/simout9
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt35
12 files changed, 45 insertions, 96 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 4b4d2436b..ee1f88977 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -22,6 +22,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
+checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@@ -36,6 +37,8 @@ decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
@@ -107,12 +110,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -281,12 +283,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -318,12 +319,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr
index ee69ae99e..eabe42249 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index cf3fc26c2..4fc3f25f8 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:55:58
+M5 compiled Feb 16 2009 00:17:12
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:45:29
M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index b1499e0a2..1bd86bd33 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 83681535 # Nu
global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted
global.BPredUnit.lookups 254458067 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-host_inst_rate 116972 # Simulator instruction rate (inst/s)
-host_mem_usage 204276 # Number of bytes of host memory used
-host_seconds 12016.73 # Real time elapsed on the host
-host_tick_rate 91760367 # Simulator tick rate (ticks/s)
+host_inst_rate 104414 # Simulator instruction rate (inst/s)
+host_mem_usage 206176 # Number of bytes of host memory used
+host_seconds 13461.92 # Real time elapsed on the host
+host_tick_rate 81909485 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit.
@@ -119,15 +119,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.001012 # ms
system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 523278 # number of replacements
system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -213,15 +204,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000004 # ms
system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 222 # number of replacements
system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -398,15 +380,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # m
system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 84497 # number of replacements
system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index 94bc4dfcb..8d0eebe28 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
+checker=Null
clock=500
cpu_id=0
defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr
index ee69ae99e..eabe42249 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
index 959e9811f..d1dad3acf 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:45:38
+M5 compiled Feb 16 2009 00:17:12
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:46:25
M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index 6ee039121..d5f28736a 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2833353 # Simulator instruction rate (inst/s)
-host_mem_usage 195884 # Number of bytes of host memory used
-host_seconds 525.71 # Real time elapsed on the host
-host_tick_rate 1416680719 # Simulator tick rate (ticks/s)
+host_inst_rate 3714547 # Simulator instruction rate (inst/s)
+host_mem_usage 197792 # Number of bytes of host memory used
+host_seconds 401.00 # Real time elapsed on the host
+host_tick_rate 1857278454 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 0.744764 # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 2760624c7..90217b2a5 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
clock=500
cpu_id=0
defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr
index ee69ae99e..eabe42249 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index 696328daa..d7c279dee 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:41:13
+M5 compiled Feb 16 2009 00:17:12
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:50:17
M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 21ee70af0..5a55fc3e0 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2121797 # Simulator instruction rate (inst/s)
-host_mem_usage 203340 # Number of bytes of host memory used
-host_seconds 702.01 # Real time elapsed on the host
-host_tick_rate 2963511011 # Simulator tick rate (ticks/s)
+host_inst_rate 1502574 # Simulator instruction rate (inst/s)
+host_mem_usage 205236 # Number of bytes of host memory used
+host_seconds 991.31 # Real time elapsed on the host
+host_tick_rate 2098643273 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 2.080416 # Number of seconds simulated
@@ -74,15 +74,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000901 # ms
system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -136,15 +127,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000001 # ms
system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 118 # number of replacements
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -219,15 +201,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # m
system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 82905 # number of replacements
system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions