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author | Kevin Lim <ktlim@umich.edu> | 2007-04-27 16:36:19 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2007-04-27 16:36:19 -0400 |
commit | 71b6499c126632766606fe227a99e06b79ddcc79 (patch) | |
tree | 10ef56b74d22307fe49d42f6747615a13197e6c0 /tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt | |
parent | 7f39291c81cb65dc166926136c8f3cab253df160 (diff) | |
download | gem5-71b6499c126632766606fe227a99e06b79ddcc79.tar.xz |
Updates for clock changes.
--HG--
extra : convert_revision : 88699ba98a738a62204ae4182f7ee5dcab9285eb
Diffstat (limited to 'tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt')
-rw-r--r-- | tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt index 41e6bfc52..7e603ae8c 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 624449 # Simulator instruction rate (inst/s) -host_mem_usage 148644 # Number of bytes of host memory used -host_seconds 2753.78 # Real time elapsed on the host -host_tick_rate 624449 # Simulator tick rate (ticks/s) +host_inst_rate 658093 # Simulator instruction rate (inst/s) +host_mem_usage 149896 # Number of bytes of host memory used +host_seconds 2613.00 # Real time elapsed on the host +host_tick_rate 329046277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1719594534 # Number of instructions simulated -sim_seconds 0.001720 # Number of seconds simulated -sim_ticks 1719594533 # Number of ticks simulated +sim_seconds 0.859797 # Number of seconds simulated +sim_ticks 859797266500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1719594534 # number of cpu cycles simulated |