diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
| commit | 0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch) | |
| tree | 96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/long/30.eon/ref | |
| parent | 1b64bfa933745294667158d0ce22180780b2a22e (diff) | |
| download | gem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz | |
Stats: Re update stats.
Diffstat (limited to 'tests/long/30.eon/ref')
21 files changed, 252 insertions, 72 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 73c8936cc..e6dd679c1 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 1688d3208..9a3fdb284 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:25:09 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:47 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index eb0b216c3..05fbc791d 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 178067 # Simulator instruction rate (inst/s) -host_mem_usage 212832 # Number of bytes of host memory used -host_seconds 2109.17 # Real time elapsed on the host -host_tick_rate 64635199 # Simulator tick rate (ticks/s) +host_inst_rate 86954 # Simulator instruction rate (inst/s) +host_mem_usage 233264 # Number of bytes of host memory used +host_seconds 4319.23 # Real time elapsed on the host +host_tick_rate 31562755 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated sim_seconds 0.136327 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 256761438 # Number of insts commited each cycle system.cpu.commit.COM:count 398664594 # Number of instructions committed +system.cpu.commit.COM:fp_insts 155295106 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 8007752 # Number of function calls committed. +system.cpu.commit.COM:int_insts 316365851 # Number of committed integer instructions. system.cpu.commit.COM:loads 94754489 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 168275218 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 272512875 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 161565122 # number of floating regfile reads +system.cpu.fp_regfile_writes 106206809 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 64427463 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 32238.031366 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 30836.486832 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 19394112 # system.cpu.iew.memOrderViolationEvents 663165 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1101512 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 5016228 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 421360455 # number of integer regfile reads +system.cpu.int_regfile_writes 182139619 # number of integer regfile writes system.cpu.ipc 1.377479 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.377479 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 272512875 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.578500 # Inst issue rate +system.cpu.iq.fp_alu_accesses 175992487 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 346671239 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 165916628 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 231922736 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 262987844 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 796105773 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 251613948 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 330463092 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 469247183 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 430384006 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ @@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 71937561 # Nu system.cpu.memDep0.conflictingStores 54246192 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 117580442 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 92914841 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 350572 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 272653822 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 10643219 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 2331141 # Number of times rename has blocked due to IQ full @@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles 96677987 # Nu system.cpu.rename.RENAME:SquashCycles 15751437 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 10596756 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 78407825 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 326649614 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 361910200 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 367264 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 37559 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 23060243 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 740781417 # The number of ROB reads +system.cpu.rob.rob_writes 1009223784 # The number of ROB writes system.cpu.timesIdled 3093 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index a541de94f..5f40a4aa8 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr index f259e0f2b..ea7dd73a3 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout index 602c1e755..96b5bf3c9 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:31:02 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index aa6437370..6fcc67a34 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4732897 # Simulator instruction rate (inst/s) -host_mem_usage 238480 # Number of bytes of host memory used -host_seconds 84.23 # Real time elapsed on the host -host_tick_rate 2366444186 # Simulator tick rate (ticks/s) +host_inst_rate 1382202 # Simulator instruction rate (inst/s) +host_mem_usage 224632 # Number of bytes of host memory used +host_seconds 288.43 # Real time elapsed on the host +host_tick_rate 691100750 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 398664824 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 398664824 # Number of busy cycles +system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses +system.cpu.num_fp_insts 155295119 # number of float instructions +system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read +system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written +system.cpu.num_func_calls 16015498 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 398664595 # Number of instructions executed -system.cpu.num_refs 168275274 # Number of memory references +system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses +system.cpu.num_int_insts 316365907 # number of integer instructions +system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read +system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written +system.cpu.num_load_insts 94754510 # Number of load instructions +system.cpu.num_mem_refs 168275274 # number of memory refs +system.cpu.num_store_insts 73520764 # Number of store instructions system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index dee4088d8..91f994c0c 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr index f259e0f2b..ea7dd73a3 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout index 3f5e4009e..4f3149cad 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:41:16 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 70d7495a6..31ad19d58 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2252516 # Simulator instruction rate (inst/s) -host_mem_usage 246196 # Number of bytes of host memory used -host_seconds 176.99 # Real time elapsed on the host -host_tick_rate 3205571054 # Simulator tick rate (ticks/s) +host_inst_rate 531142 # Simulator instruction rate (inst/s) +host_mem_usage 232344 # Number of bytes of host memory used +host_seconds 750.58 # Real time elapsed on the host +host_tick_rate 755872580 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567343 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1134686340 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1134686340 # Number of busy cycles +system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses +system.cpu.num_fp_insts 155295119 # number of float instructions +system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read +system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written +system.cpu.num_func_calls 16015498 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 398664609 # Number of instructions executed -system.cpu.num_refs 168275276 # Number of memory references +system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses +system.cpu.num_int_insts 316365921 # number of integer instructions +system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read +system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written +system.cpu.num_load_insts 94754511 # Number of load instructions +system.cpu.num_mem_refs 168275276 # number of memory refs +system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini index 05c074be9..5e5332f9b 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 026fec0e6..da6bef881 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 03:29:33 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:35 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index 432c33c36..6d2d3d9a2 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 100561 # Simulator instruction rate (inst/s) -host_mem_usage 266348 # Number of bytes of host memory used -host_seconds 3428.53 # Real time elapsed on the host -host_tick_rate 62832373 # Simulator tick rate (ticks/s) +host_inst_rate 72451 # Simulator instruction rate (inst/s) +host_mem_usage 252856 # Number of bytes of host memory used +host_seconds 4758.76 # Real time elapsed on the host +host_tick_rate 45268689 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 344777955 # Number of instructions simulated sim_seconds 0.215423 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 417225954 # Number of insts commited each cycle system.cpu.commit.COM:count 344777955 # Number of instructions committed +system.cpu.commit.COM:fp_insts 114216705 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 283262899 # Number of committed integer instructions. system.cpu.commit.COM:loads 94652977 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 177028572 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 430736614 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 185889152 # number of floating regfile reads +system.cpu.fp_regfile_writes 130863264 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 45676058 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 11498.094859 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 7998.634691 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 11245258 # system.cpu.iew.memOrderViolationEvents 6487 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 2859204 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 7562654 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 857434842 # number of integer regfile reads +system.cpu.int_regfile_writes 187420899 # number of integer regfile writes system.cpu.ipc 0.800235 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.800235 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 430736614 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.876078 # Inst issue rate +system.cpu.iq.fp_alu_accesses 122762429 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 242026964 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 116081453 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 130324765 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 261691284 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 951420966 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 249709151 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 308466887 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 389801085 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 377454477 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 3540937 # Number of non-speculative instructions added to the IQ @@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 34606299 # Nu system.cpu.memDep0.conflictingStores 43565672 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 108215524 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 93620853 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1021297951 # number of misc regfile reads +system.cpu.misc_regfile_writes 43097547 # number of misc regfile writes system.cpu.numCycles 430845860 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 2009946 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 340171955 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 2410 # Number of times rename has blocked due to IQ full @@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles 159405057 # Nu system.cpu.rename.RENAME:SquashCycles 13510660 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 15892138 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 73676716 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 836456573 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 842367236 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 117198109 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 12788197 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 37692287 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 3543781 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 805385527 # The number of ROB reads +system.cpu.rob.rob_writes 800205983 # The number of ROB writes system.cpu.timesIdled 2211 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 191 # Number of system calls diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini index ac380ff0f..a5b41f00b 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout index f5391da34..934921226 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:19:59 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt index 4b61fce38..f26b1f1eb 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2280191 # Simulator instruction rate (inst/s) -host_mem_usage 262416 # Number of bytes of host memory used -host_seconds 151.21 # Real time elapsed on the host -host_tick_rate 1390158822 # Simulator tick rate (ticks/s) +host_inst_rate 829275 # Simulator instruction rate (inst/s) +host_mem_usage 237784 # Number of bytes of host memory used +host_seconds 415.76 # Real time elapsed on the host +host_tick_rate 505582613 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 344777955 # Number of instructions simulated sim_seconds 0.210200 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 420400644 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 420400644 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses +system.cpu.num_fp_insts 114216705 # number of float instructions +system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read +system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 344777955 # Number of instructions executed -system.cpu.num_refs 177028576 # Number of memory references +system.cpu.num_int_alu_accesses 283262903 # Number of integer alu accesses +system.cpu.num_int_insts 283262903 # number of integer instructions +system.cpu.num_int_register_reads 1207980255 # number of times the integer registers were read +system.cpu.num_int_register_writes 211974282 # number of times the integer registers were written +system.cpu.num_load_insts 94652977 # Number of load instructions +system.cpu.num_mem_refs 177028576 # number of memory refs +system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.workload.PROG:num_syscalls 191 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini index 3b627362e..9c15d1771 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr index 0de362399..fc990d9e5 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr @@ -1,12 +1,20 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data processing 8parts -Grid measure is 6 by 3.0001 by 6 +Grid measure is warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +6 by 3.0001 by 6 cell dimension is 0.863065 Creating grid for list of length 21 Grid size = 7 by 4 by 7 diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout index 26d019ac6..1f52687a3 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:23:59 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:00:13 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt index 9ac8b63de..b6636f892 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 520438 # Simulator instruction rate (inst/s) -host_mem_usage 270128 # Number of bytes of host memory used -host_seconds 661.75 # Real time elapsed on the host -host_tick_rate 794599336 # Simulator tick rate (ticks/s) +host_inst_rate 394687 # Simulator instruction rate (inst/s) +host_mem_usage 245492 # Number of bytes of host memory used +host_seconds 872.59 # Real time elapsed on the host +host_tick_rate 602604420 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 344399678 # Number of instructions simulated sim_seconds 0.525826 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1051651768 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1051651768 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses +system.cpu.num_fp_insts 114216705 # number of float instructions +system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read +system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 344399678 # Number of instructions executed -system.cpu.num_refs 177028576 # Number of memory references +system.cpu.num_int_alu_accesses 283262902 # Number of integer alu accesses +system.cpu.num_int_insts 283262902 # number of integer instructions +system.cpu.num_int_register_reads 1344047799 # number of times the integer registers were read +system.cpu.num_int_register_writes 212263713 # number of times the integer registers were written +system.cpu.num_load_insts 94652977 # Number of load instructions +system.cpu.num_mem_refs 177028576 # number of memory refs +system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.workload.PROG:num_syscalls 191 # Number of system calls ---------- End Simulation Statistics ---------- |