diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 02:20:40 -0500 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 02:20:40 -0500 |
commit | 8833b4cd44457d50b45a4dfe642cdb5e51c0889d (patch) | |
tree | 64417a9e2d759dc367848de4b7ee117b3903dc54 /tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt | |
parent | ec1a4cbbc73ecc1d7456d11c571c425e226a7d3b (diff) | |
download | gem5-8833b4cd44457d50b45a4dfe642cdb5e51c0889d.tar.xz |
Bus: Update the stats for the recent bus fix.
--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt')
-rw-r--r-- | tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt | 100 |
1 files changed, 50 insertions, 50 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index c79bac28f..69139eb9a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 890836 # Simulator instruction rate (inst/s) -host_mem_usage 328448 # Number of bytes of host memory used -host_seconds 2042.78 # Real time elapsed on the host -host_tick_rate 1270245606 # Simulator tick rate (ticks/s) +host_inst_rate 1098189 # Simulator instruction rate (inst/s) +host_mem_usage 373972 # Number of bytes of host memory used +host_seconds 1657.07 # Real time elapsed on the host +host_tick_rate 1574114309 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated -sim_seconds 2.594831 # Number of seconds simulated -sim_ticks 2594830590000 # Number of ticks simulated +sim_seconds 2.608424 # Number of seconds simulated +sim_ticks 2608424230000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16114.256812 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14114.256812 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 17373.778213 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14373.778213 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 116383834000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 125480619000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 101939006000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 103813377000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 26999.842958 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.842958 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 56195050000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 60690301000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 51699446000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 53946895000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18223.331337 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16223.331337 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 19658.571674 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16658.571674 # average overall mshr miss latency system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 172578884000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 186170920000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 153638452000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 157760272000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18223.331337 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16223.331337 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 19658.571674 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16658.571674 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 595853949 # number of overall hits -system.cpu.dcache.overall_miss_latency 172578884000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 186170920000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses system.cpu.dcache.overall_misses 9470216 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 153638452000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 157760272000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.310460 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.381693 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40726989000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 40744129000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.dtb.accesses 611922547 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 160728502 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 20050000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 21654000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 18446000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 19248000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 20050000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 21654000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 802 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 18446000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 19248000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1826377708 # number of overall hits -system.cpu.icache.overall_miss_latency 20050000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 21654000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 802 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 18446000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 19248000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.506560 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.562745 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,28 +160,28 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 1826378510 # ITB hits system.cpu.itb.misses 18 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 41565040000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 43454360000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 20782520000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 41253806000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 43128979000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 20626903000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 21978.336430 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 22977.351722 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 7878838000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 8236967000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3943302000 # number of UpgradeReq MSHR miss cycles @@ -198,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 82818846000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 86583339000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -212,11 +212,11 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5348043 # number of overall hits -system.cpu.l2cache.overall_miss_latency 82818846000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 86583339000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses system.cpu.l2cache.overall_misses 3764493 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2751986 # number of replacements system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25384.669947 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 25389.772813 # Cycle average of tags in use system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 571912424000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 574940849000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1194738 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5189661180 # number of cpu cycles simulated +system.cpu.numCycles 5216848460 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed system.cpu.num_refs 613169725 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls |