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author | Joel Hestness <jthestness@gmail.com> | 2015-10-10 16:45:41 -0500 |
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committer | Joel Hestness <jthestness@gmail.com> | 2015-10-10 16:45:41 -0500 |
commit | 735c4a87665119a33443cf8d191d329c66191c6e (patch) | |
tree | 619a6c346beb6f7972acfa41a737b065f6c701c5 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | |
parent | 1f2e7c1aaa17e55b06504264e40bde1a000f2214 (diff) | |
download | gem5-735c4a87665119a33443cf8d191d329c66191c6e.tar.xz |
stats: Update for UDelayEvent quiesce change
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 468bf5591..538ad9900 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.474700 # Nu sim_ticks 47474700369500 # Number of ticks simulated final_tick 47474700369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 631720 # Simulator instruction rate (inst/s) -host_op_rate 743100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34016391858 # Simulator tick rate (ticks/s) -host_mem_usage 766400 # Number of bytes of host memory used -host_seconds 1395.64 # Real time elapsed on the host +host_inst_rate 794386 # Simulator instruction rate (inst/s) +host_op_rate 934446 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42775515400 # Simulator tick rate (ticks/s) +host_mem_usage 715280 # Number of bytes of host memory used +host_seconds 1109.86 # Real time elapsed on the host sim_insts 881655060 # Number of instructions simulated sim_ops 1037101350 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -557,6 +557,8 @@ system.cpu0.itb.accesses 441266366 # DT system.cpu0.numCycles 94949400739 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 5268 # number of quiesce instructions executed system.cpu0.committedInsts 440958495 # Number of instructions committed system.cpu0.committedOps 519578987 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 478066113 # Number of integer alu accesses @@ -614,8 +616,6 @@ system.cpu0.op_class::MemWrite 76133369 14.64% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 519868732 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 7168 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 5565465 # number of replacements system.cpu0.dcache.tags.tagsinuse 503.695844 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 153367622 # Total number of references to valid blocks. @@ -1545,6 +1545,8 @@ system.cpu1.itb.accesses 441061279 # DT system.cpu1.numCycles 94949400719 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 13508 # number of quiesce instructions executed system.cpu1.committedInsts 440696565 # Number of instructions committed system.cpu1.committedOps 517522363 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 474820793 # Number of integer alu accesses @@ -1602,8 +1604,6 @@ system.cpu1.op_class::MemWrite 74675005 14.42% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 517832459 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14490 # number of quiesce instructions executed system.cpu1.dcache.tags.replacements 5147651 # number of replacements system.cpu1.dcache.tags.tagsinuse 420.489425 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 152204564 # Total number of references to valid blocks. |