diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
commit | 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch) | |
tree | 64b85031cb791a21af6059778384d358d992b817 /tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt | |
parent | dbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff) | |
download | gem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz |
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt')
-rw-r--r-- | tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 250 |
1 files changed, 125 insertions, 125 deletions
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index d610f9b78..40a365e11 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu sim_ticks 361488530000 # Number of ticks simulated final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1414417 # Simulator instruction rate (inst/s) -host_op_rate 1414475 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2096975339 # Simulator tick rate (ticks/s) -host_mem_usage 357072 # Number of bytes of host memory used -host_seconds 172.39 # Real time elapsed on the host +host_inst_rate 1027753 # Simulator instruction rate (inst/s) +host_op_rate 1027796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1523718944 # Simulator tick rate (ticks/s) +host_mem_usage 413792 # Number of bytes of host memory used +host_seconds 237.24 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory @@ -128,126 +128,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 935475 # number of replacements -system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use -system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits -system.cpu.dcache.overall_hits::total 104182817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses -system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks -system.cpu.dcache.writebacks::total 935266 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks. @@ -384,5 +264,125 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 935475 # number of replacements +system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use +system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits +system.cpu.dcache.overall_hits::total 104182817 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses +system.cpu.dcache.overall_misses::total 939567 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks +system.cpu.dcache.writebacks::total 935266 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |