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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
commit | 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch) | |
tree | 64b85031cb791a21af6059778384d358d992b817 /tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | |
parent | dbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff) | |
download | gem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz |
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt')
-rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index c5e407e29..ee0778484 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.024415 # Nu sim_ticks 24414646000 # Number of ticks simulated final_tick 24414646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171645 # Simulator instruction rate (inst/s) -host_op_rate 171645 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52651835 # Simulator tick rate (ticks/s) -host_mem_usage 254848 # Number of bytes of host memory used -host_seconds 463.70 # Real time elapsed on the host +host_inst_rate 131517 # Simulator instruction rate (inst/s) +host_op_rate 131517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40342582 # Simulator tick rate (ticks/s) +host_mem_usage 309584 # Number of bytes of host memory used +host_seconds 605.18 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 490368 # Number of bytes read from this memory @@ -192,6 +192,15 @@ system.physmem.writeRowHits 40821 # Nu system.physmem.readRowHitRate 91.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate 35.80 # Row buffer hit rate for writes system.physmem.avgGap 87091.78 # Average gap between requests +system.cpu.branchPred.lookups 16536427 # Number of BP lookups +system.cpu.branchPred.condPredicted 10675204 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 418905 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11705282 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7341882 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 62.722812 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1987114 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 42052 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 4583 # Nu system.cpu.numCycles 48829295 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16536427 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10675204 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 418905 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11705282 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7341882 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1987114 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 42052 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 15791672 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 105370615 # Number of instructions fetch has processed system.cpu.fetch.Branches 16536427 # Number of branches that fetch encountered |