diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 2556 |
1 files changed, 1278 insertions, 1278 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 5ac1aa00b..6256fdd50 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,1282 +1,1282 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.787836 # Number of seconds simulated -sim_ticks 787835965500 # Number of ticks simulated -final_tick 787835965500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263266 # Simulator instruction rate (inst/s) -host_op_rate 283629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 134283963 # Simulator tick rate (ticks/s) -host_mem_usage 329624 # Number of bytes of host memory used -host_seconds 5866.94 # Real time elapsed on the host -sim_insts 1544563024 # Number of instructions simulated -sim_ops 1664032416 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 236015808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63804544 # Number of bytes read from this memory -system.physmem.bytes_read::total 299885696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104593152 # Number of bytes written to this memory -system.physmem.bytes_written::total 104593152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1021 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3687747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 996946 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4685714 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634268 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634268 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 82941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 299574808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 80987092 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380644841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 82941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 82941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 132760062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 132760062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 132760062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 82941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 299574808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 80987092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 513404904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4685714 # Number of read requests accepted -system.physmem.writeReqs 1634268 # Number of write requests accepted -system.physmem.readBursts 4685714 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634268 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 299374336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 511360 # Total number of bytes read from write queue -system.physmem.bytesWritten 104589440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299885696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104593152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7990 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 28 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301500 # Per bank write bursts -system.physmem.perBankRdBursts::1 301960 # Per bank write bursts -system.physmem.perBankRdBursts::2 285447 # Per bank write bursts -system.physmem.perBankRdBursts::3 288137 # Per bank write bursts -system.physmem.perBankRdBursts::4 288946 # Per bank write bursts -system.physmem.perBankRdBursts::5 285921 # Per bank write bursts -system.physmem.perBankRdBursts::6 281288 # Per bank write bursts -system.physmem.perBankRdBursts::7 278400 # Per bank write bursts -system.physmem.perBankRdBursts::8 294011 # Per bank write bursts -system.physmem.perBankRdBursts::9 300115 # Per bank write bursts -system.physmem.perBankRdBursts::10 292046 # Per bank write bursts -system.physmem.perBankRdBursts::11 297684 # Per bank write bursts -system.physmem.perBankRdBursts::12 299531 # Per bank write bursts -system.physmem.perBankRdBursts::13 298464 # Per bank write bursts -system.physmem.perBankRdBursts::14 294115 # Per bank write bursts -system.physmem.perBankRdBursts::15 290159 # Per bank write bursts -system.physmem.perBankWrBursts::0 103775 # Per bank write bursts -system.physmem.perBankWrBursts::1 101738 # Per bank write bursts -system.physmem.perBankWrBursts::2 99347 # Per bank write bursts -system.physmem.perBankWrBursts::3 99748 # Per bank write bursts -system.physmem.perBankWrBursts::4 99113 # Per bank write bursts -system.physmem.perBankWrBursts::5 98946 # Per bank write bursts -system.physmem.perBankWrBursts::6 102275 # Per bank write bursts -system.physmem.perBankWrBursts::7 103989 # Per bank write bursts -system.physmem.perBankWrBursts::8 105110 # Per bank write bursts -system.physmem.perBankWrBursts::9 104316 # Per bank write bursts -system.physmem.perBankWrBursts::10 101973 # Per bank write bursts -system.physmem.perBankWrBursts::11 102390 # Per bank write bursts -system.physmem.perBankWrBursts::12 102662 # Per bank write bursts -system.physmem.perBankWrBursts::13 102242 # Per bank write bursts -system.physmem.perBankWrBursts::14 104082 # Per bank write bursts -system.physmem.perBankWrBursts::15 102504 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 787835924500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4685714 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634268 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2727826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1050681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 326941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 233426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 158423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 90275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 39813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 72860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 104977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 109635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 109963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 109142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4259361 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.841028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.814946 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.698820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3400000 79.82% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 662329 15.55% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94740 2.22% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35136 0.82% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22172 0.52% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12513 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7488 0.18% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5149 0.12% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19834 0.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4259361 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98005 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.729004 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.044358 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95588 97.53% 97.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1180 1.20% 98.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 706 0.72% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 397 0.41% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 101 0.10% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 3 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98005 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.674761 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.634865 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.202481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 70360 71.79% 71.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1982 2.02% 73.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17660 18.02% 91.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5209 5.32% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1729 1.76% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 596 0.61% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 225 0.23% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 114 0.12% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 71 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 31 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 17 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98005 # Writes before turning the bus around for reads -system.physmem.totQLat 162836208305 # Total ticks spent queuing -system.physmem.totMemAccLat 250543533305 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23388620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34810.99 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53560.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 132.76 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.01 # Data bus utilization in percentage -system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing -system.physmem.readRowHits 1712017 # Number of row buffer hits during reads -system.physmem.writeRowHits 340548 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 20.84 # Row buffer hit rate for writes -system.physmem.avgGap 124657.94 # Average gap between requests -system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15118935720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8035889730 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16504816860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4222619820 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 59457815040.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64415436660 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1624122240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 222796740750 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 36224267040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 16152645360 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 444563646270 # Total energy per rank (pJ) -system.physmem_0.averagePower 564.284526 # Core power per rank (mW) -system.physmem_0.totalIdleTime 642315388170 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1436139102 # Time in different power states -system.physmem_0.memoryStateTime::REF 25173062000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 59398115500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 94331998561 # Time in different power states -system.physmem_0.memoryStateTime::ACT 118911366978 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 488585283359 # Time in different power states -system.physmem_1.actEnergy 15292958940 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8128385265 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 16894132500 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4307956380 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 58918161120.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64834688190 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616111040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 219342669570 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 35641510560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18222503400 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 443208649005 # Total energy per rank (pJ) -system.physmem_1.averagePower 562.564626 # Core power per rank (mW) -system.physmem_1.totalIdleTime 641423107931 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1455389769 # Time in different power states -system.physmem_1.memoryStateTime::REF 24945910000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67593570250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 92814429154 # Time in different power states -system.physmem_1.memoryStateTime::ACT 120009883050 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 481016783277 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286288991 # Number of BP lookups -system.cpu.branchPred.condPredicted 223379889 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14638803 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157014468 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150316303 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.734046 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16636731 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3547 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2042 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1505 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1575671932 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13942337 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067450540 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286288991 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166955076 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1546978368 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29302455 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1029 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656906223 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 925 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1575573272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.405744 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.233501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 493163312 31.30% 31.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465492881 29.54% 60.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101391668 6.44% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515525411 32.72% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1575573272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.181693 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.312107 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74679257 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 578142352 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849952798 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58148325 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14650540 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 135611620 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 746 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037153887 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52516232 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14650540 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139761664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 493000122 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16309 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837842196 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 90302441 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976324662 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26749907 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45308958 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126668 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1624936 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 29276583 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985726338 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127758695 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432766069 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 161 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310827393 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 177 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111376144 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542477238 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199268014 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26870545 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28963209 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947887828 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 229 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857408251 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13517769 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283855641 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647022412 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 59 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1575573272 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.178878 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 622703787 39.52% 39.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326030740 20.69% 60.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378156304 24.00% 84.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219671219 13.94% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29004864 1.84% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6358 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1575573272 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166096777 40.98% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2401 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191354081 47.22% 88.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47812478 11.80% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138249696 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 803001 0.04% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 34 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532063614 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186291823 10.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 37 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857408251 # Type of FU issued -system.cpu.iq.rate 1.178804 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405265784 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218189 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5709173052 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231756417 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805664221 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 288 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 75 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262673874 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17815816 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84170904 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66799 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13274 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24420969 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4535474 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4852528 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14650540 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25426885 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1470128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947888203 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542477238 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199268014 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 167 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159099 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1309527 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13274 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7696809 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8718333 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16415142 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827780120 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516898840 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29628131 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 146 # number of nop insts executed -system.cpu.iew.exec_refs 698650840 # number of memory reference insts executed -system.cpu.iew.exec_branches 229565077 # Number of branches executed -system.cpu.iew.exec_stores 181752000 # Number of stores executed -system.cpu.iew.exec_rate 1.160000 # Inst execution rate -system.cpu.iew.wb_sent 1808693799 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805664296 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169145221 # num instructions producing a value -system.cpu.iew.wb_consumers 1689395973 # num instructions consuming a value -system.cpu.iew.wb_rate 1.145965 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692049 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 257953466 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14638116 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1536081048 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.083297 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.009309 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 955788021 62.22% 62.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250630730 16.32% 78.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110093475 7.17% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55285008 3.60% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29278263 1.91% 91.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34064309 2.22% 93.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24750177 1.61% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18104449 1.18% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58086616 3.78% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1536081048 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563042 # Number of instructions committed -system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 633153379 # Number of memory references committed -system.cpu.commit.loads 458306334 # Number of loads committed -system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462427 # Number of branches committed -system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. -system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 174847021 10.51% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58086616 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3399979733 # The number of ROB reads -system.cpu.rob.rob_writes 3883469027 # The number of ROB writes -system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98660 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563024 # Number of Instructions Simulated -system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.020141 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.020141 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980257 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980257 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175723378 # number of integer regfile reads -system.cpu.int_regfile_writes 1261531313 # number of integer regfile writes -system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 57 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965468307 # number of cc regfile reads -system.cpu.cc_regfile_writes 551796531 # number of cc regfile writes -system.cpu.misc_regfile_reads 675796862 # number of misc regfile reads -system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17001793 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963908 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638014747 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17002305 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 81846500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963908 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335598455 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335598455 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469297691 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469297691 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168716899 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168716899 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638014590 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638014590 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638014590 # number of overall hits -system.cpu.dcache.overall_hits::total 638014590 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17414213 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17414213 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3869148 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3869148 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21283361 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21283361 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21283363 # number of overall misses -system.cpu.dcache.overall_misses::total 21283363 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 440649629000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 440649629000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157410000348 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157410000348 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 389500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 389500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 598059629348 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 598059629348 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 598059629348 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 598059629348 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486711904 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486711904 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659297951 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659297951 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659297953 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659297953 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022419 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022419 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25304.022008 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25304.022008 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40683.375345 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40683.375345 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 97375 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 97375 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28099.867749 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28099.867749 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28099.865108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28099.865108 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21246265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3823077 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 940794 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67416 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.583334 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.708749 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17001793 # number of writebacks -system.cpu.dcache.writebacks::total 17001793 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149457 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3149457 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1131591 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1131591 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14264756 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14264756 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737557 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737557 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17002313 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17002313 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17002314 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17002314 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354315671500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 354315671500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121139018143 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 121139018143 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475454689643 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 475454689643 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475454764643 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 475454764643 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24838.537126 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24838.537126 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44250.774739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44250.774739 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27964.118155 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27964.118155 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27964.120922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27964.120922 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 591 # number of replacements -system.cpu.icache.tags.tagsinuse 443.744305 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656904625 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 611074.069767 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 443.744305 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.866688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.866688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313813517 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313813517 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656904625 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656904625 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656904625 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656904625 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656904625 # number of overall hits -system.cpu.icache.overall_hits::total 656904625 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1596 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1596 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1596 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1596 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1596 # number of overall misses -system.cpu.icache.overall_misses::total 1596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 121940986 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 121940986 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 121940986 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 121940986 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 121940986 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 121940986 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656906221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656906221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656906221 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656906221 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656906221 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656906221 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76404.126566 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76404.126566 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76404.126566 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76404.126566 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 19802 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 105.893048 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 33.600000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 591 # number of writebacks -system.cpu.icache.writebacks::total 591 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 520 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 520 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 520 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 520 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 520 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 520 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 89957490 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 89957490 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 89957490 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 89957490 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 89957490 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 89957490 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83603.615242 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83603.615242 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 11616550 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11644306 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 18561 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 1 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4655502 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 4647569 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15870.791949 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13265757 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4663475 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.844608 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15652.012265 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 218.779684 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.955323 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013353 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968676 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 135 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15771 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4017 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7150 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2693 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1496 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008240 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962585 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561731761 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561731761 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 4837264 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 4837264 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 12143869 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 12143869 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1756642 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1756642 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 54 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 54 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11509702 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 11509702 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 54 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13266344 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13266398 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 54 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13266344 # number of overall hits -system.cpu.l2cache.overall_hits::total 13266398 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 980963 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 980963 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1022 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1022 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2754998 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2754998 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3735961 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3736983 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1022 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3735961 # number of overall misses -system.cpu.l2cache.overall_misses::total 3736983 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 191500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 191500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104504427500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 104504427500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 88486500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 88486500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256725449000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 256725449000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 88486500 # number of demand (read+write) miss cycles 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UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 9 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737605 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737605 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14264700 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 14264700 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17002305 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17003381 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17002305 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17003381 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358329 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.358329 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.949814 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.949814 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193134 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193134 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.949814 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.219733 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.219779 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.949814 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.219733 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.219779 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21277.777778 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21277.777778 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106532.486444 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106532.486444 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86581.702544 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86581.702544 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93185.348592 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93185.348592 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86581.702544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96689.948450 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 96687.184020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86581.702544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96689.948450 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 96687.184020 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 58080 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 1634268 # number of writebacks -system.cpu.l2cache.writebacks::total 1634268 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3942 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3942 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45595 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45595 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 49537 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 49538 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 49537 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 49538 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1199044 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1199044 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 977021 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 977021 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1021 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1021 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709403 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709403 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1021 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3686424 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3687445 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1021 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3686424 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1199044 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4886489 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84363300436 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 137500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 137500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98257390500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98257390500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 82266500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 82266500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237433882500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237433882500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 82266500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335691273000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 335773539500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 82266500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335691273000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 420136839936 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356889 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356889 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.948885 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189938 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189938 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216865 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.287383 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70358.802876 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100568.350629 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100568.350629 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80574.436827 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80574.436827 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.283974 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.283974 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91058.589213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85979.286956 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34005774 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17002402 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21251 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 202098 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 202097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14265775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6471532 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12165120 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3013301 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1495847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14264700 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51006435 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51009177 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176263168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176369792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6143430 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104594048 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 23146806 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009650 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097758 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22923448 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 223357 0.96% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23146806 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34005271029 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 21045 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25503465992 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 9333292 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 4668829 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3708542 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634268 # Transaction distribution -system.membus.trans_dist::CleanEvict 3013301 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 977171 # Transaction distribution -system.membus.trans_dist::ReadExResp 977171 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3708543 # Transaction distribution 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# Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4685723 # Request fanout histogram -system.membus.reqLayer0.occupancy 17639856241 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25447920698 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.2 # Layer utilization (%) +sim_seconds 0.787836 +sim_ticks 787835965500 +final_tick 787835965500 +sim_freq 1000000000000 +host_inst_rate 147468 +host_op_rate 158874 +host_tick_rate 75218875 +host_mem_usage 340272 +host_seconds 10473.91 +sim_insts 1544563024 +sim_ops 1664032416 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500 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100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 4685723 +system.membus.reqLayer0.occupancy 17639856241 +system.membus.reqLayer0.utilization 2.2 +system.membus.respLayer1.occupancy 25447920698 +system.membus.respLayer1.utilization 3.2 ---------- End Simulation Statistics ---------- |