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author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | |
parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt')
-rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index a7912f8e0..60e11bdef 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042005 # Nu sim_ticks 42005374000 # Number of ticks simulated final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106867 # Simulator instruction rate (inst/s) -host_op_rate 106867 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48844875 # Simulator tick rate (ticks/s) -host_mem_usage 218932 # Number of bytes of host memory used -host_seconds 859.98 # Real time elapsed on the host +host_inst_rate 160903 # Simulator instruction rate (inst/s) +host_op_rate 160903 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73542430 # Simulator tick rate (ticks/s) +host_mem_usage 222752 # Number of bytes of host memory used +host_seconds 571.17 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -322,9 +322,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 52276.878093 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7264 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 7269 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.213285 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.214808 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor |