diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
| commit | e63c73b45d688c7af7a1a3ed01dbde538c57acc2 (patch) | |
| tree | b10b8bbf9dd89f219c5c63ab9d2d745924935425 /tests/quick/00.hello/ref/alpha/linux | |
| parent | fc746c2268bfceded0014749cddd8234fa55a35a (diff) | |
| download | gem5-e63c73b45d688c7af7a1a3ed01dbde538c57acc2.tar.xz | |
BPRED: Update regressions for tournament predictor fix.
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux')
5 files changed, 374 insertions, 374 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 94e787873..3181a01cf 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 10 2010 23:42:32 -M5 revision 1633bdfc3b0a 7062 default qtip regression_update tip -M5 started Apr 10 2010 23:42:34 -M5 executing on zooks +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:43:43 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 31225500 because target called exit() +Exiting @ tick 31242000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index adbfbe35c..8b050d9d7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30166 # Simulator instruction rate (inst/s) -host_mem_usage 153332 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 146878557 # Simulator tick rate (ticks/s) +host_inst_rate 29156 # Simulator instruction rate (inst/s) +host_mem_usage 203904 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 142052352 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31225500 # Number of ticks simulated +sim_ticks 31242000 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 2050 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 202 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 582 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBHits 94 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 314 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 125 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 957 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condIncorrect 895 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 751 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 6537 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.instReqsProcessed 6554 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 721 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 345 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.predictedNotTaken 829 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 237 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 125 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 6537 # Number of Instructions Requests that completed in this resource. +system.cpu.Decode-Unit.instReqsProcessed 6554 # Number of Instructions Requests that completed in this resource. system.cpu.Execution-Unit.cyclesExecuted 4340 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 4354 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 447 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 165 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.069493 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 13895 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 524 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 134 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.utilization 0.069457 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 13850 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 6404 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 2 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 1 # Number of Multiply Requests Processed. system.cpu.RegFile-Manager.instReqsProcessed 19960 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 22.223468 # Percentage of cycles cpu is active +system.cpu.activity 22.272545 # Percentage of cycles cpu is active system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.752030 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.752030 # CPI: Total CPI of All Threads +system.cpu.cpi 9.757183 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.757183 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56342.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53342.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56336.842105 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53336.842105 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5352500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5352000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5067500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5067000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56063.218391 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53063.218391 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56057.471264 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53057.471264 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4877500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4877000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4616500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4616000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +66,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56208.791209 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53208.791209 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56203.296703 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53203.296703 # average overall mshr miss latency system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10230000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10229000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9684000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9683000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025299 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 103.624059 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025306 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.651945 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56208.791209 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53208.791209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56203.296703 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53203.296703 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10230000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10229000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses system.cpu.dcache.overall_misses 182 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9684000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9683000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,7 +98,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 103.624059 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.651945 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -119,73 +119,73 @@ system.cpu.dtb.write_accesses 868 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 7358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55544.850498 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52868.421053 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 7057 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16719000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.040908 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 7296 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55536.544850 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52863.157895 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6995 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16716500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.041255 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 301 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15067500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.038733 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 15066000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.039062 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 24.848592 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 24.630282 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7358 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55544.850498 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52868.421053 # average overall mshr miss latency -system.cpu.icache.demand_hits 7057 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16719000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.040908 # miss rate for demand accesses +system.cpu.icache.demand_accesses 7296 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55536.544850 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency +system.cpu.icache.demand_hits 6995 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16716500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.041255 # miss rate for demand accesses system.cpu.icache.demand_misses 301 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15067500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.038733 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 15066000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.039062 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.063597 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 130.247335 # Average occupied blocks per context -system.cpu.icache.overall_accesses 7358 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55544.850498 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52868.421053 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.063623 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 130.299954 # Average occupied blocks per context +system.cpu.icache.overall_accesses 7296 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55536.544850 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 7057 # number of overall hits -system.cpu.icache.overall_miss_latency 16719000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.040908 # miss rate for overall accesses +system.cpu.icache.overall_hits 6995 # number of overall hits +system.cpu.icache.overall_miss_latency 16716500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.041255 # miss rate for overall accesses system.cpu.icache.overall_misses 301 # number of overall misses system.cpu.icache.overall_mshr_hits 16 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15067500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.038733 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 15066000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.039062 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 130.247335 # Cycle average of tags in use -system.cpu.icache.total_refs 7057 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 130.299954 # Cycle average of tags in use +system.cpu.icache.total_refs 6995 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 7356 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 48573 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.102543 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.102543 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 7294 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 48568 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.102489 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.102489 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 7375 # ITB accesses +system.cpu.itb.fetch_accesses 7313 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 7358 # ITB hits +system.cpu.itb.fetch_hits 7296 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -196,19 +196,19 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52061.643836 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52054.794521 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3800500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3800000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52069.920844 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52065.963061 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39944.591029 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19734500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19733000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15139000 # number of ReadReq MSHR miss cycles @@ -232,10 +232,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 453 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52068.584071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52064.159292 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23535000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 23533000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997792 # miss rate for demand accesses system.cpu.l2cache.demand_misses 452 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -245,14 +245,14 @@ system.cpu.l2cache.demand_mshr_misses 452 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 181.381905 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005537 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 181.445272 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52068.584071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52064.159292 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23535000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 23533000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997792 # miss rate for overall accesses system.cpu.l2cache.overall_misses 452 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -264,32 +264,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.381905 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 181.445272 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 62452 # number of cpu cycles simulated -system.cpu.runCycles 13879 # Number of cycles cpu stages are processed. +system.cpu.numCycles 62485 # number of cpu cycles simulated +system.cpu.runCycles 13917 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 55077 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 7375 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 11.809069 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 55915 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 6537 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.467239 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 55982 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 55172 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 7313 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 11.703609 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 55931 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 6554 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 10.488917 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 56015 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.359956 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 60399 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 10.354485 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 60432 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.287325 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 56048 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.285589 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 56081 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.254275 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 62452 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 10.248860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 62485 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 1b5a762f3..409d22ab8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 0bdde157a..2c74abf7c 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:54 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 01:04:08 -M5 executing on SC2B0619 -command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:59:38 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12474500 because target called exit() +Exiting @ tick 12497500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 7fffd3b0b..1208848c5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,259 +1,259 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 104903 # Simulator instruction rate (inst/s) -host_mem_usage 190976 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 203948336 # Simulator tick rate (ticks/s) +host_inst_rate 84020 # Simulator instruction rate (inst/s) +host_mem_usage 204400 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 163850067 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12474500 # Number of ticks simulated +sim_ticks 12497500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 806 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1370 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2263 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1337 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2245 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 315 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12417 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.515664 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.304890 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 12431 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.515083 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.305811 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 9514 76.62% 76.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1627 13.10% 89.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 488 3.93% 93.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 267 2.15% 95.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 153 1.23% 97.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% 97.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 9528 76.65% 76.65% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1629 13.10% 89.75% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 491 3.95% 93.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 259 2.08% 95.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 156 1.25% 97.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% 97.88% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77% 98.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 53 0.43% 99.07% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 115 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 49 0.39% 99.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 119 0.96% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12417 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12431 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2050 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4622 # The number of squashed insts skipped by commit system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses +system.cpu.cpi 3.914187 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.914187 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1782 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34993.902439 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1618 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5739000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.092031 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 164 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056678 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35082.894737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35729.885057 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 13331500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3108500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.275862 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses -system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2647 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35056.066176 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2103 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 19070500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.205516 # miss rate for demand accesses +system.cpu.dcache.demand_misses 544 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6770500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.071024 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.026922 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 110.270477 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 110.050975 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2647 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35056.066176 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2104 # number of overall hits -system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses -system.cpu.dcache.overall_misses 554 # number of overall misses -system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 2103 # number of overall hits +system.cpu.dcache.overall_miss_latency 19070500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.205516 # miss rate for overall accesses +system.cpu.dcache.overall_misses 544 # number of overall misses +system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6770500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.071024 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use -system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 110.050975 # Cycle average of tags in use +system.cpu.dcache.total_refs 2136 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 1123 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 188 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12474 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8945 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2313 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 900 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 2951 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 2948 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2890 # DTB hits +system.cpu.dtb.data_hits 2887 # DTB hits system.cpu.dtb.data_misses 61 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1876 # DTB read accesses +system.cpu.dtb.read_accesses 1865 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1840 # DTB read hits +system.cpu.dtb.read_hits 1829 # DTB read hits system.cpu.dtb.read_misses 36 # DTB read misses -system.cpu.dtb.write_accesses 1075 # DTB write accesses +system.cpu.dtb.write_accesses 1083 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1050 # DTB write hits +system.cpu.dtb.write_hits 1058 # DTB write hits system.cpu.dtb.write_misses 25 # DTB write misses -system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched -system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 501 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 13314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.995268 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.362110 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2245 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1792 # Number of cache lines fetched +system.cpu.fetch.Cycles 4238 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13309 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.089814 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1792 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1007 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.532445 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13331 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.998350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.390717 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 10844 81.45% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 252 1.89% 83.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 238 1.79% 85.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 230 1.73% 86.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 272 2.04% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 162 1.22% 90.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 232 1.74% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 129 0.97% 92.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 955 7.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 10920 81.91% 81.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 245 1.84% 83.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 221 1.66% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 185 1.39% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 233 1.75% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 164 1.23% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 228 1.71% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 133 1.00% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1002 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13314 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 13331 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1792 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35303.990610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1366 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15039500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.237723 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.171317 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.449511 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency -system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses -system.cpu.icache.demand_misses 424 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 1792 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency +system.cpu.icache.demand_hits 1366 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15039500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.237723 # miss rate for demand accesses +system.cpu.icache.demand_misses 426 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.171317 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077417 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 158.550695 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.077094 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 157.888110 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1792 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1378 # number of overall hits -system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses -system.cpu.icache.overall_misses 424 # number of overall misses -system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1366 # number of overall hits +system.cpu.icache.overall_miss_latency 15039500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.237723 # miss rate for overall accesses +system.cpu.icache.overall_misses 426 # number of overall misses +system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.171317 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use -system.cpu.icache.total_refs 1378 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 157.888110 # Cycle average of tags in use +system.cpu.icache.total_refs 1366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1450 # Number of branches executed -system.cpu.iew.EXEC:nop 82 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate -system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1077 # Number of stores executed +system.cpu.idleCycles 11665 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1448 # Number of branches executed +system.cpu.iew.EXEC:nop 83 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.362498 # Inst execution rate +system.cpu.iew.EXEC:refs 2956 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1085 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 6020 # num instructions consuming a value -system.cpu.iew.WB:count 8734 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back +system.cpu.iew.WB:consumers 6049 # num instructions consuming a value +system.cpu.iew.WB:count 8759 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.745247 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4491 # num instructions producing a value -system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle -system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 4508 # num instructions producing a value +system.cpu.iew.WB:rate 0.350416 # insts written-back per cycle +system.cpu.iew.WB:sent 8858 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 427 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 73 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2269 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11059 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1871 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 304 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 9061 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 900 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores @@ -262,77 +262,77 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1084 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 406 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.255481 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.255481 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6254 66.92% 66.94% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 66.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1986 21.25% 88.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1100 11.77% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6287 67.13% 67.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1968 21.01% 88.20% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1105 11.80% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9345 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 9365 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 92 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009824 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 14 13.33% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 56 53.33% 66.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 35 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.09% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 56 60.87% 61.96% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.04% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 13314 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.701893 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302449 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13331 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.702498 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.304735 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 9113 68.45% 68.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1716 12.89% 81.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 1071 8.04% 89.38% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 725 5.45% 94.82% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 355 2.67% 97.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 172 1.29% 98.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 115 0.86% 99.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.26% 99.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 9142 68.58% 68.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1697 12.73% 81.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 1062 7.97% 89.27% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 730 5.48% 94.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 359 2.69% 97.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 188 1.41% 98.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 105 0.79% 99.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 36 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 13314 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate -system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 13331 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.374660 # Inst issue rate +system.cpu.iq.iqInstsAdded 10951 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9365 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4181 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2504 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1838 # ITB accesses +system.cpu.itb.fetch_accesses 1827 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 1802 # ITB hits -system.cpu.itb.fetch_misses 36 # ITB misses +system.cpu.itb.fetch_hits 1792 # ITB hits +system.cpu.itb.fetch_misses 35 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -342,31 +342,31 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.753425 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31376.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2516000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2290500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34418.918919 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31239.557740 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14008500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12714500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -378,31 +378,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34426.041667 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16524500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15005000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006558 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 214.901533 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006535 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 214.135921 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34426.041667 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16524500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15005000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -410,32 +410,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 214.135921 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 24950 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2269 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 24996 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 340 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed -system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 9098 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 255 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15174 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 12043 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8961 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2203 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 900 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 292 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4378 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 498 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 750 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- |