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authorNathan Binkert <binkertn@umich.edu>2007-06-12 07:56:53 -0700
committerNathan Binkert <binkertn@umich.edu>2007-06-12 07:56:53 -0700
commit1a3e668446e4b2d2c61651c9ae58e643c2aa3ad2 (patch)
treec1a0811248e7d8addf4e84d3532e5d506e8aaec8 /tests/quick/00.hello/ref/alpha/tru64
parent125237d357be7f2c5adf03da8dcf352ccad32954 (diff)
downloadgem5-1a3e668446e4b2d2c61651c9ae58e643c2aa3ad2.tar.xz
update for small parameter and statistics name changes
--HG-- extra : convert_revision : d538b79986c11a462ab285c167cef45dd793da32
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64')
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out6
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt11
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini2
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt7
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out6
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt7
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout8
11 files changed, 38 insertions, 41 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 40a8f1a84..e3080f9e5 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -99,7 +99,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -274,7 +274,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -312,7 +312,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -366,7 +366,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
index 46dc2c36a..0cb6591c8 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
@@ -275,7 +275,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
-prefetch_latency=10
+prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@@ -312,7 +312,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
-prefetch_latency=10
+prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@@ -349,7 +349,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
-prefetch_latency=10
+prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
index c1b1b7625..6dd4c291d 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,9 @@ global.BPredUnit.condIncorrect 208 # Nu
global.BPredUnit.condPredicted 376 # Number of conditional branches predicted
global.BPredUnit.lookups 738 # Number of BP lookups
global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target.
-host_inst_rate 54176 # Simulator instruction rate (inst/s)
-host_mem_usage 153592 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-host_tick_rate 46286693 # Simulator tick rate (ticks/s)
+host_inst_rate 8881 # Simulator instruction rate (inst/s)
+host_seconds 0.27 # Real time elapsed on the host
+host_tick_rate 7632084 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit.
@@ -268,7 +267,7 @@ system.cpu.ipc 0.580920 # IP
system.cpu.ipc_total 0.580920 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 0 0.00% # Type of FU issued
+ No_OpClass 0 0.00% # Type of FU issued
IntAlu 2178 70.83% # Type of FU issued
IntMult 1 0.03% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
@@ -286,7 +285,7 @@ system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
+ No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 2 5.71% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index 587034bb2..60520dc0c 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled May 14 2007 16:35:50
-M5 started Tue May 15 12:18:41 2007
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
+M5 compiled Jun 10 2007 14:06:20
+M5 started Sun Jun 10 14:22:36 2007
+M5 executing on iceaxe
+command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2053000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 20dfddd0a..61db8446a 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -53,7 +53,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
index e82d837af..29351d427 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 484860 # Simulator instruction rate (inst/s)
-host_mem_usage 147796 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 225459318 # Simulator tick rate (ticks/s)
+host_inst_rate 111994 # Simulator instruction rate (inst/s)
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 55017079 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
index 3b5348194..f76500526 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled May 14 2007 16:35:50
-M5 started Tue May 15 12:18:42 2007
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
+M5 compiled Jun 10 2007 14:06:20
+M5 started Sun Jun 10 14:22:37 2007
+M5 executing on iceaxe
+command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1288500 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 1c1daa355..5a336ab13 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -44,7 +44,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -82,7 +82,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -120,7 +120,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -174,7 +174,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
index 45a8521ac..241630ead 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
@@ -94,7 +94,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
-prefetch_latency=10
+prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@@ -131,7 +131,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
-prefetch_latency=10
+prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@@ -168,7 +168,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
-prefetch_latency=10
+prefetch_latency=100000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index 756244d02..621520fa3 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 228404 # Simulator instruction rate (inst/s)
-host_mem_usage 153176 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 552831639 # Simulator tick rate (ticks/s)
+host_inst_rate 51133 # Simulator instruction rate (inst/s)
+host_seconds 0.05 # Real time elapsed on the host
+host_tick_rate 127514531 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index f5e3a6008..1c6780cf0 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled May 14 2007 16:35:50
-M5 started Tue May 15 12:18:42 2007
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
+M5 compiled Jun 10 2007 14:06:20
+M5 started Sun Jun 10 14:22:37 2007
+M5 executing on iceaxe
+command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 6472000 because target called exit()